[4.4.y,04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources

Message ID	1557761837-24993-5-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <cip-dev-bounces@lists.cip-project.org> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> To: cip-dev@lists.cip-project.org Date: Mon, 13 May 2019 16:36:29 +0100 Message-Id: <1557761837-24993-5-git-send-email-fabrizio.castro@bp.renesas.com> In-Reply-To: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1557761837-24993-1-git-send-email-fabrizio.castro@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 4.4.y 04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org
Series	Add basic support for the iwg23s \| expand [4.4.y,00/52] Add basic support for the iwg23s [4.4.y,01/52] ARM: shmobile: r8a77470: basic SoC support [4.4.y,02/52] clk: shmobile: rcar-gen2: Add quirks for the RZ/G1C [4.4.y,03/52] clk: shmobile: Compile clk-rcar-gen2.c when using the r8a77470 [4.4.y,04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources [4.4.y,05/52] pinctrl: sh-pfc: Add r8a77470 PFC support [4.4.y,06/52] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups [4.4.y,07/52] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups [4.4.y,08/52] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups [4.4.y,09/52] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups [4.4.y,10/52] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups [4.4.y,11/52] pinctrl: sh-pfc: r8a77470: Add USB pin groups [4.4.y,12/52] pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groups [4.4.y,13/52] pinctrl: sh-pfc: r8a77470: Add DU1 pin groups [4.4.y,14/52] pinctrl: sh-pfc: r8a77470: Add VIN pin groups [4.4.y,15/52] pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups [4.4.y,16/52] soc: renesas: rcar-rst: Add support for RZ/G1C [4.4.y,17/52] ARM: debug-ll: Add support for r8a77470 [4.4.y,18/52] gpiolib: Extract mask allocation into subroutine [4.4.y,19/52] gpiolib: Support 'gpio-reserved-ranges' property [4.4.y,20/52] gpiolib: Avoid calling chip->request() for unused gpios [4.4.y,21/52] gpio: rcar: Implement gpiochip.set_multiple() [4.4.y,22/52] gpio: rcar: Add GPIO hole support [4.4.y,23/52] dt-bindings: gpio: Add a gpio-reserved-ranges property [4.4.y,24/52] dt-bindings: gpio: rcar: Add gpio-reserved-ranges support [4.4.y,25/52] ARM: shmobile: defconfig: Enable r8a77470 SoC [4.4.y,26/52] ARM: multi_v7_defconfig: Enable r8a77470 SoC [4.4.y,27/52] serial: sh-sci: Document r8a77470 bindings [4.4.y,28/52] dt-bindings: sram: Document renesas, smp-sram [4.4.y,29/52] ARM: dts: r8a77470: Initial SoC device tree [4.4.y,30/52] clk: shmobile: Document r8a77470 CPG clock support [4.4.y,31/52] clk: shmobile: Document r8a77470 CPG DIV6 clock support [4.4.y,32/52] clk: shmobile: Document r8a77470 MSTP clock support [4.4.y,33/52] ARM: dts: r8a77470: Add clocks [4.4.y,34/52] dt-bindings: arm: Document iW-RainboW-G23S single board computer [4.4.y,35/52] ARM: dts: iwg23s-sbc: Add support for iWave G23S-SBC based on RZ/G1C [4.4.y,36/52] dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC support [4.4.y,37/52] ARM: dts: r8a77470: Add PFC support [4.4.y,38/52] dt-bindings: gpio: rcar: Add r8a77470 (RZ/G1C) support [4.4.y,39/52] ARM: dts: r8a77470: Add GPIO support [4.4.y,40/52] ARM: dts: r8a77470: Add SCIF support [4.4.y,41/52] dt-bindings: irqchip: renesas-irqc: Document r8a77470 support [4.4.y,42/52] ARM: dts: r8a77470: Add IRQC support [4.4.y,43/52] ARM: dts: iwg23s-sbc: Add pinctl support for scif1 [4.4.y,44/52] dt-bindings: rcar-dmac: Document missing error interrupt [4.4.y,45/52] dt-bindings: rcar-dmac: Document r8a77470 support [4.4.y,46/52] ARM: dts: r8a77470: Add SYS-DMAC support [4.4.y,47/52] ARM: dts: r8a77470: Add SCIF DMA support [4.4.y,48/52] dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC [4.4.y,49/52] ARM: dts: r8a77470: Add EtherAVB support [4.4.y,50/52] ARM: dts: iwg23s-sbc: Add EtherAVB support [4.4.y,51/52] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ [4.4.y,52/52] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB

diff --git a/include/dt-bindings/clock/r8a77470-clock.h b/include/dt-bindings/clock/r8a77470-clock.h new file mode 100644 index 0000000..2f20bcc --- /dev/null +++ b/include/dt-bindings/clock/r8a77470-clock.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2019 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A77470_H__ +#define __DT_BINDINGS_CLOCK_R8A77470_H__ + +/* CPG */ +#define R8A77470_CLK_MAIN 0 +#define R8A77470_CLK_PLL0 1 +#define R8A77470_CLK_PLL1 2 +#define R8A77470_CLK_PLL3 3 +#define R8A77470_CLK_LB 4 +#define R8A77470_CLK_QSPI 5 +#define R8A77470_CLK_SDH 6 +#define R8A77470_CLK_SD0 7 +#define R8A77470_CLK_SD1 8 +#define R8A77470_CLK_RCAN 9 + +/* MSTP0 */ +#define R8A77470_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A77470_CLK_VCP0 1 +#define R8A77470_CLK_VPC0 3 +#define R8A77470_CLK_STB 4 +#define R8A77470_CLK_TMU1 11 +#define R8A77470_CLK_3DG 12 +#define R8A77470_CLK_2DDMAC 15 +#define R8A77470_CLK_FDP1_0 19 +#define R8A77470_CLK_TMU3 21 +#define R8A77470_CLK_TMU2 22 +#define R8A77470_CLK_CMT0 24 +#define R8A77470_CLK_VSP1DU0 28 +#define R8A77470_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A77470_CLK_MSIOF2 5 +#define R8A77470_CLK_MSIOF1 8 +#define R8A77470_CLK_SYS_DMAC1 18 +#define R8A77470_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A77470_CLK_SDHI2 12 +#define R8A77470_CLK_SDHI1 13 +#define R8A77470_CLK_SDHI0 14 +#define R8A77470_CLK_USBHS_DMAC0_CH1 26 +#define R8A77470_CLK_USBHS_DMAC1_CH1 27 +#define R8A77470_CLK_CMT1 29 +#define R8A77470_CLK_USBHS_DMAC0_CH0 30 +#define R8A77470_CLK_USBHS_DMAC1_CH0 31 + +/* MSTP4 */ +#define R8A77470_CLK_RWDT 2 +#define R8A77470_CLK_USB_DDM0 6 +#define R8A77470_CLK_IRQC 7 +#define R8A77470_CLK_INTC_SYS 8 +#define R8A77470_CLK_USB_DDM1 9 + +/* MSTP5 */ +#define R8A77470_CLK_AUDIO_DMAC0 2 +#define R8A77470_CLK_PWM 23 +#define R8A77470_CLK_BOOT_ROM 30 + +/* MSTP7 */ +#define R8A77470_CLK_USB_EHCI_0 3 +#define R8A77470_CLK_USBHS0 4 +#define R8A77470_CLK_USB_EHCI_1 5 +#define R8A77470_CLK_USBHS1 6 +#define R8A77470_CLK_HSCIF2 13 +#define R8A77470_CLK_SCIF5 14 +#define R8A77470_CLK_SCIF4 15 +#define R8A77470_CLK_HSCIF1 16 +#define R8A77470_CLK_HSCIF0 17 +#define R8A77470_CLK_SCIF3 18 +#define R8A77470_CLK_SCIF2 19 +#define R8A77470_CLK_SCIF1 20 +#define R8A77470_CLK_SCIF0 21 +#define R8A77470_CLK_DU1 23 +#define R8A77470_CLK_DU0 24 +#define R8A77470_CLK_LVDS 26 +#define R8A77470_CLK_DVE 27 + +/* MSTP8 */ +#define R8A77470_CLK_IPMMU_SGX 0 +#define R8A77470_CLK_DVD 1 +#define R8A77470_CLK_VIN1 10 +#define R8A77470_CLK_VIN0 11 +#define R8A77470_CLK_ETHERAVB 12 +#define R8A77470_CLK_ETHER 13 + +/* MSTP9 */ +#define R8A77470_CLK_IR_RECEIVER 3 +#define R8A77470_CLK_GPIO5 7 +#define R8A77470_CLK_GPIO4 8 +#define R8A77470_CLK_GPIO3 9 +#define R8A77470_CLK_GPIO2 10 +#define R8A77470_CLK_GPIO1 11 +#define R8A77470_CLK_GPIO0 12 +#define R8A77470_CLK_CAN1 15 +#define R8A77470_CLK_CAN0 16 +#define R8A77470_CLK_QUAD_SPI1 17 +#define R8A77470_CLK_QUAD_SPI0 18 +#define R8A77470_CLK_ADG 22 +#define R8A77470_CLK_I2C4 27 +#define R8A77470_CLK_I2C3 28 +#define R8A77470_CLK_I2C2 29 +#define R8A77470_CLK_I2C1 30 +#define R8A77470_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A77470_CLK_SSI_ALL 5 +#define R8A77470_CLK_SSI9 6 +#define R8A77470_CLK_SSI8 7 +#define R8A77470_CLK_SSI7 8 +#define R8A77470_CLK_SSI6 9 +#define R8A77470_CLK_SSI5 10 +#define R8A77470_CLK_SSI4 11 +#define R8A77470_CLK_SSI3 12 +#define R8A77470_CLK_SSI2 13 +#define R8A77470_CLK_SSI1 14 +#define R8A77470_CLK_SSI0 15 +#define R8A77470_CLK_SCU_ALL 17 +#define R8A77470_CLK_SCU_DVC1 18 +#define R8A77470_CLK_SCU_DVC0 19 +#define R8A77470_CLK_SCU_CTU1_MIX1 20 +#define R8A77470_CLK_SCU_CTU0_MIX0 21 +#define R8A77470_CLK_SCU_SRC6 25 +#define R8A77470_CLK_SCU_SRC5 26 +#define R8A77470_CLK_SCU_SRC4 27 +#define R8A77470_CLK_SCU_SRC3 28 +#define R8A77470_CLK_SCU_SRC2 29 +#define R8A77470_CLK_SCU_SRC1 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A77470_H__ */

[4.4.y,04/52] ARM: shmobile: r8a77470: Add clock index macros for DT sources

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