diff mbox series

[06/21] drm/i915: Convert some more bits to use engine mmio accessors

Message ID 20190606093639.9372-7-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Implicit dev_priv removal | expand

Commit Message

Tvrtko Ursulin June 6, 2019, 9:36 a.m. UTC 
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Remove a couple dev_priv locals as a consequence.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 27 ++++++++++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.c         |  5 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c       |  2 +-
 drivers/gpu/drm/i915/i915_reg.h             |  2 +-
 drivers/gpu/drm/i915/intel_guc_submission.c |  4 +--
 5 files changed, 20 insertions(+), 20 deletions(-)

Comments

Chris Wilson June 6, 2019, 9:53 a.m. UTC | #1 
Quoting Tvrtko Ursulin (2019-06-06 10:36:24)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Remove a couple dev_priv locals as a consequence.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c         | 27 ++++++++++-----------
>  drivers/gpu/drm/i915/i915_gem_gtt.c         |  5 ++--
>  drivers/gpu/drm/i915/i915_gpu_error.c       |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h             |  2 +-
>  drivers/gpu/drm/i915/intel_guc_submission.c |  4 +--
>  5 files changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index fed704802c57..f27b6c002627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  
>  static void enable_execlists(struct intel_engine_cs *engine)
>  {
> -       struct drm_i915_private *dev_priv = engine->i915;
> -
>         intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>  
> -       if (INTEL_GEN(dev_priv) >= 11)
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
> +       if (INTEL_GEN(engine->i915) >= 11)
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
>         else
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>  
> -       I915_WRITE(RING_MI_MODE(engine->mmio_base),
> -                  _MASKED_BIT_DISABLE(STOP_RING));
> +       ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>  
> -       I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> -                  i915_ggtt_offset(engine->status_page.vma));
> -       POSTING_READ(RING_HWS_PGA(engine->mmio_base));
> +       ENGINE_WRITE(engine,
> +                    RING_HWS_PGA,
> +                    i915_ggtt_offset(engine->status_page.vma));
> +       ENGINE_POSTING_READ(engine, RING_HWS_PGA);
>  }
>  
>  static bool unexpected_starting_state(struct intel_engine_cs *engine)
>  {
> -       struct drm_i915_private *dev_priv = engine->i915;
>         bool unexpected = false;
>  
> -       if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
> +       if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
>                 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
>                 unexpected = true;
>         }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0fe568cfabe0..3ba970f2db28 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1713,8 +1713,9 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>  
>         for_each_engine(engine, dev_priv, id) {
>                 /* GFX_MODE is per-ring on gen7+ */
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>         }
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f85de034d8f..193a93857d99 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>         if (HAS_PPGTT(dev_priv)) {
>                 int i;
>  
> -               ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> +               ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
>  
>                 if (IS_GEN(dev_priv, 6)) {
>                         ee->vm_info.pp_dir_base =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b9ae48d1abe..8a8b34a13d2e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2698,7 +2698,7 @@ enum i915_power_well_id {
>  
>  #define GFX_MODE       _MMIO(0x2520)
>  #define GFX_MODE_GEN7  _MMIO(0x229c)
> -#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
> +#define RING_MODE_GEN7(base)   _MMIO((base) + 0x29c)
>  #define   GFX_RUN_LIST_ENABLE          (1 << 15)
>  #define   GFX_INTERRUPT_STEERING       (1 << 14)
>  #define   GFX_TLB_INVALIDATE_EXPLICIT  (1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index a4f98ccef0fe..89592ef778b8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1306,7 +1306,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
>          */
>         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
>         for_each_engine(engine, dev_priv, id)
> -               I915_WRITE(RING_MODE_GEN7(engine), irqs);
> +               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>  
>         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
>         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> @@ -1353,7 +1353,7 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
>         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
>         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
>         for_each_engine(engine, dev_priv, id)
> -               I915_WRITE(RING_MODE_GEN7(engine), irqs);
> +               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>  
>         /* route all GT interrupts to the host */
>         I915_WRITE(GUC_BCS_RCS_IER, 0);

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fed704802c57..f27b6c002627 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2021,31 +2021,30 @@  static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 
 static void enable_execlists(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
-
 	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+	if (INTEL_GEN(engine->i915) >= 11)
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
 	else
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 
-	I915_WRITE(RING_MI_MODE(engine->mmio_base),
-		   _MASKED_BIT_DISABLE(STOP_RING));
+	ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
 
-	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
-		   i915_ggtt_offset(engine->status_page.vma));
-	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
+	ENGINE_WRITE(engine,
+		     RING_HWS_PGA,
+		     i915_ggtt_offset(engine->status_page.vma));
+	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
 }
 
 static bool unexpected_starting_state(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
 	bool unexpected = false;
 
-	if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
+	if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
 		DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
 		unexpected = true;
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0fe568cfabe0..3ba970f2db28 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1713,8 +1713,9 @@  static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 
 	for_each_engine(engine, dev_priv, id) {
 		/* GFX_MODE is per-ring on gen7+ */
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2f85de034d8f..193a93857d99 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1219,7 +1219,7 @@  static void error_record_engine_registers(struct i915_gpu_state *error,
 	if (HAS_PPGTT(dev_priv)) {
 		int i;
 
-		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
+		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
 
 		if (IS_GEN(dev_priv, 6)) {
 			ee->vm_info.pp_dir_base =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b9ae48d1abe..8a8b34a13d2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2698,7 +2698,7 @@  enum i915_power_well_id {
 
 #define GFX_MODE	_MMIO(0x2520)
 #define GFX_MODE_GEN7	_MMIO(0x229c)
-#define RING_MODE_GEN7(engine)	_MMIO((engine)->mmio_base + 0x29c)
+#define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
 #define   GFX_RUN_LIST_ENABLE		(1 << 15)
 #define   GFX_INTERRUPT_STEERING	(1 << 14)
 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index a4f98ccef0fe..89592ef778b8 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1306,7 +1306,7 @@  static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 	 */
 	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 	for_each_engine(engine, dev_priv, id)
-		I915_WRITE(RING_MODE_GEN7(engine), irqs);
+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
 	/* route USER_INTERRUPT to Host, all others are sent to GuC. */
 	irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -1353,7 +1353,7 @@  static void guc_interrupts_release(struct drm_i915_private *dev_priv)
 	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
 	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
 	for_each_engine(engine, dev_priv, id)
-		I915_WRITE(RING_MODE_GEN7(engine), irqs);
+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
 	/* route all GT interrupts to the host */
 	I915_WRITE(GUC_BCS_RCS_IER, 0);