| Message ID | 20190606093639.9372-10-tvrtko.ursulin@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implicit dev_priv removal | expand |
Quoting Tvrtko Ursulin (2019-06-06 10:36:27) > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Continuing the conversion and elimination of implicit dev_priv. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++++++++++++----------- > drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- > 4 files changed, 21 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 0e9b74f52503..3554d0dd7b1a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) > > RUNTIME_INFO(i915)->num_engines = hweight32(mask); > > - i915_check_and_clear_faults(i915); > + i915_check_and_clear_faults(&i915->uncore); I am not sold on that. Especially as it is then unwrapped back to i915. -Chris
On 06/06/2019 10:57, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2019-06-06 10:36:27) >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> Continuing the conversion and elimination of implicit dev_priv. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- >> drivers/gpu/drm/i915/i915_drv.c | 2 +- >> drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ++++++++++++----------- >> drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- >> 4 files changed, 21 insertions(+), 19 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> index 0e9b74f52503..3554d0dd7b1a 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) >> >> RUNTIME_INFO(i915)->num_engines = hweight32(mask); >> >> - i915_check_and_clear_faults(i915); >> + i915_check_and_clear_faults(&i915->uncore); > > I am not sold on that. Especially as it is then unwrapped back to i915. It isn't really, not on the logical level. This is the body: void i915_check_and_clear_faults(struct intel_uncore *uncore) { struct drm_i915_private *i915 = uncore_to_i915(uncore); /* From GEN8 onwards we only have one 'All Engine Fault Register' */ if (INTEL_GEN(i915) >= 8) gen8_check_faults(uncore); else if (INTEL_GEN(i915) >= 6) gen6_check_faults(uncore); else return; uncore_clear_error_registers(uncore, ALL_ENGINES); } So the idea being i915 is used only for "what gen am I checkes", while the actual functionality operates on uncore. Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 0e9b74f52503..3554d0dd7b1a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) RUNTIME_INFO(i915)->num_engines = hweight32(mask); - i915_check_and_clear_faults(i915); + i915_check_and_clear_faults(&i915->uncore); intel_setup_engine_capabilities(i915); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1af6751e1b36..72acd5bc5101 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2340,7 +2340,7 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_uncore_resume_early(&dev_priv->uncore); - i915_check_and_clear_faults(dev_priv); + i915_check_and_clear_faults(&dev_priv->uncore); if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) { gen9_sanitize_dc_state(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 3ba970f2db28..0cecc43a64b0 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2299,14 +2299,14 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active(); } -static void gen6_check_faults(struct drm_i915_private *dev_priv) +static void gen6_check_faults(struct intel_uncore *uncore) { struct intel_engine_cs *engine; enum intel_engine_id id; - u32 fault; - for_each_engine(engine, dev_priv, id) { - fault = GEN6_RING_FAULT_REG_READ(engine); + for_each_engine(engine, uncore_to_i915(uncore), id) { + u32 fault = GEN6_RING_FAULT_REG_READ(engine); + if (fault & RING_FAULT_VALID) { DRM_DEBUG_DRIVER("Unexpected fault\n" "\tAddr: 0x%08lx\n" @@ -2321,16 +2321,16 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv) } } -static void gen8_check_faults(struct drm_i915_private *dev_priv) +static void gen8_check_faults(struct intel_uncore *uncore) { - u32 fault = I915_READ(GEN8_RING_FAULT_REG); + u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG); if (fault & RING_FAULT_VALID) { u32 fault_data0, fault_data1; u64 fault_addr; - fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); - fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); + fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0); + fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1); fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | ((u64)fault_data0 << 12); @@ -2349,17 +2349,19 @@ static void gen8_check_faults(struct drm_i915_private *dev_priv) } } -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) +void i915_check_and_clear_faults(struct intel_uncore *uncore) { + struct drm_i915_private *i915 = uncore_to_i915(uncore); + /* From GEN8 onwards we only have one 'All Engine Fault Register' */ - if (INTEL_GEN(dev_priv) >= 8) - gen8_check_faults(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) - gen6_check_faults(dev_priv); + if (INTEL_GEN(i915) >= 8) + gen8_check_faults(uncore); + else if (INTEL_GEN(i915) >= 6) + gen6_check_faults(uncore); else return; - uncore_clear_error_registers(&dev_priv->uncore, ALL_ENGINES); + uncore_clear_error_registers(uncore, ALL_ENGINES); } void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) @@ -2372,7 +2374,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) < 6) return; - i915_check_and_clear_faults(dev_priv); + i915_check_and_clear_faults(&dev_priv->uncore); ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total); @@ -3650,7 +3652,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) struct i915_ggtt *ggtt = &dev_priv->ggtt; struct i915_vma *vma, *vn; - i915_check_and_clear_faults(dev_priv); + i915_check_and_clear_faults(&dev_priv->uncore); mutex_lock(&ggtt->vm.mutex); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 152a03560c22..9ac701988030 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -649,7 +649,7 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base); -void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); +void i915_check_and_clear_faults(struct intel_uncore *uncore); void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);