| Message ID | 20190214083145.15148-1-benjamin.gaignard@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | ARM errata 814220 | expand |
On 2/14/19 9:31 AM, Benjamin Gaignard wrote: > Implement ARM errata 814220 for Cortex A7. > > This patch has been wroten by Jason Liu years ago but never send upstream. > I have tried to contact the author on multiple email addresses but I haven't > found any valid one... > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > version 2: > - limite help lines to 80 columns. > - Add Arnd Bergmann acks. > > Benjamin Gaignard (2): > ARM: errata 814220-B-Cache maintenance by set/way operations can > execute out of order. > ARM: stm32: select ARM errata 814220 > > arch/arm/Kconfig | 12 ++++++++++++ > arch/arm/mach-stm32/Kconfig | 1 + > arch/arm/mm/cache-v7.S | 3 +++ > 3 files changed, 16 insertions(+) > Russel, If you agree, can I take this series in my STM32 soc tree ? If yes it will be part of my PR for v5.2. regards Alex
On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue <alexandre.torgue@st.com> wrote: > > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote: > > Implement ARM errata 814220 for Cortex A7. > > > > This patch has been wroten by Jason Liu years ago but never send upstream. > > I have tried to contact the author on multiple email addresses but I haven't > > found any valid one... > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. Adding Jason's NXP e-mail address. Thanks
Le mar. 23 avr. 2019 à 19:46, Fabio Estevam <festevam@gmail.com> a écrit : > > On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue > <alexandre.torgue@st.com> wrote: > > > > > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote: > > > Implement ARM errata 814220 for Cortex A7. > > > > > > This patch has been wroten by Jason Liu years ago but never send upstream. > > > I have tried to contact the author on multiple email addresses but I haven't > > > found any valid one... > > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > Adding Jason's NXP e-mail address. Thanks ! Russell, can Alexandre push this series in stm32 tree or you prefer to merge it yourself ? Regards, Benjamin > > Thanks
Le mer. 24 avr. 2019 à 09:25, Benjamin Gaignard <benjamin.gaignard@linaro.org> a écrit : > > Le mar. 23 avr. 2019 à 19:46, Fabio Estevam <festevam@gmail.com> a écrit : > > > > On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue > > <alexandre.torgue@st.com> wrote: > > > > > > > > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote: > > > > Implement ARM errata 814220 for Cortex A7. > > > > > > > > This patch has been wroten by Jason Liu years ago but never send upstream. > > > > I have tried to contact the author on multiple email addresses but I haven't > > > > found any valid one... > > > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > > > Adding Jason's NXP e-mail address. > Thanks ! > > Russell, can Alexandre push this series in stm32 tree or you prefer to > merge it yourself ? > Hello Russell, I have push this series in your patch system weeks ago, but nothing happens. Do I miss something in your process ? Regards, Benjamin > Regards, > Benjamin > > > > Thanks
On Tue, Jun 11, 2019 at 01:42:34PM +0200, Benjamin Gaignard wrote: > Le mer. 24 avr. 2019 à 09:25, Benjamin Gaignard > <benjamin.gaignard@linaro.org> a écrit : > > > > Le mar. 23 avr. 2019 à 19:46, Fabio Estevam <festevam@gmail.com> a écrit : > > > > > > On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue > > > <alexandre.torgue@st.com> wrote: > > > > > > > > > > > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote: > > > > > Implement ARM errata 814220 for Cortex A7. > > > > > > > > > > This patch has been wroten by Jason Liu years ago but never send upstream. > > > > > I have tried to contact the author on multiple email addresses but I haven't > > > > > found any valid one... > > > > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6. > > > > > > Adding Jason's NXP e-mail address. > > Thanks ! > > > > Russell, can Alexandre push this series in stm32 tree or you prefer to > > merge it yourself ? > > > > Hello Russell, > > I have push this series in your patch system weeks ago, but nothing happens. > Do I miss something in your process ? I'm now running stuff on a shoe-string here, so I only process patches once or twice a release cycle. That's what happens when your funding gets severely cut - we are now _really_ struggling as a business, and so I don't see the current situation being able to be maintained much further into the future (our income is no longer sufficient to sustain us as a business.) However, I'll get to it in the next couple of weeks.
Implement ARM errata 814220 for Cortex A7. This patch has been wroten by Jason Liu years ago but never send upstream. I have tried to contact the author on multiple email addresses but I haven't found any valid one... I have keep Jason's sign-off and just rebase the patch on to v5-rc6. version 2: - limite help lines to 80 columns. - Add Arnd Bergmann acks. Benjamin Gaignard (2): ARM: errata 814220-B-Cache maintenance by set/way operations can execute out of order. ARM: stm32: select ARM errata 814220 arch/arm/Kconfig | 12 ++++++++++++ arch/arm/mach-stm32/Kconfig | 1 + arch/arm/mm/cache-v7.S | 3 +++ 3 files changed, 16 insertions(+)