| Message ID | 1558366019-24214-3-git-send-email-gerald.baeza@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | stm32-ddr-pmu driver creation | expand |
On Mon, 20 May 2019 15:27:16 +0000, Gerald BAEZA wrote: > The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. > > This documentation indicates how to enable stm32-ddr-pmu driver on > DDRPERFM peripheral, via the device tree. > > Signed-off-by: Gerald Baeza <gerald.baeza@st.com> > --- > .../devicetree/bindings/perf/stm32-ddr-pmu.txt | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt new file mode 100644 index 0000000..9d36209 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt @@ -0,0 +1,20 @@ +* STM32 DDR Performance Monitor (DDRPERFM) + +Required properties: +- compatible: must be "st,stm32-ddr-pmu". +- reg: physical address and length of the registers set. +- clocks: list of phandles and specifiers to all input clocks listed in + clock-names property. +- clock-names: "bus" corresponds to the DDRPERFM bus clock and "ddr" to + the DDR frequency. +- resets: phandle to the reset controller and DDRPERFM reset specifier + +Example: + ddrperfm: perf@5a007000 { + compatible = "st,stm32-ddr-pmu"; + reg = <0x5a007000 0x400>; + clocks = <&rcc DDRPERFM>, <&rcc PLL2_R>; + clock-names = "bus", "ddr"; + resets = <&rcc DDRPERFM_R>; + }; +
The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. This documentation indicates how to enable stm32-ddr-pmu driver on DDRPERFM peripheral, via the device tree. Signed-off-by: Gerald Baeza <gerald.baeza@st.com> --- .../devicetree/bindings/perf/stm32-ddr-pmu.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt