| Message ID | 20190522161921.20750-2-nm@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Initial support Texas Instrument's J721E Platform | expand |
On Wed, May 22, 2019 at 11:19:16AM -0500, Nishanth Menon wrote: > The J721E SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable lower system costs > of automotive applications such as infotainment, cluster, premium > Audio, Gateway, industrial and a range of broad market applications. > This SoC is designed around reducing the system cost by eliminating > the need of an external system MCU and is targeted towards ASIL-B/C > certification/requirements in addition to allowing complex software > and system use-cases. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, three clusters of lockstep > capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), > C7x floating point Vector DSP, Two C66x floating point DSPs. > * 3D GPU PowerVR Rogue 8XE GE8430 > * Vision Processing Accelerator (VPAC) with image signal processor and Depth > and Motion Processing Accelerator (DMPAC) > * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual > PRUs and dual RTUs > * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and > up to two DPI interfaces. > * Integrated Ethernet switch supporting up to a total of 8 external ports in > addition to legacy Ethernet switch of up to 2 ports. > * System MMU (SMMU) Version 3.0 and advanced virtualisation > capabilities. > * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, > 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, > I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > * Configurable L3 Cache and IO-coherent architecture with high data throughput > capable distributed DMA architecture under NAVSS > * Centralized System Controller for Security, Power, and Resource > Management (DMSC) > > See J721E Technical Reference Manual (SPRUIL1, May 2019) > for further details: http://www.ti.com/lit/pdf/spruil1 > > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ > 1 file changed, 3 insertions(+) Okay for now, but please convert K3 and other TI SoCs to schema soon. Reviewed-by: Rob Herring <robh@kernel.org>
On Wed, 22 May 2019 11:19:16 -0500, Nishanth Menon wrote: > The J721E SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable lower system costs > of automotive applications such as infotainment, cluster, premium > Audio, Gateway, industrial and a range of broad market applications. > This SoC is designed around reducing the system cost by eliminating > the need of an external system MCU and is targeted towards ASIL-B/C > certification/requirements in addition to allowing complex software > and system use-cases. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, three clusters of lockstep > capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), > C7x floating point Vector DSP, Two C66x floating point DSPs. > * 3D GPU PowerVR Rogue 8XE GE8430 > * Vision Processing Accelerator (VPAC) with image signal processor and Depth > and Motion Processing Accelerator (DMPAC) > * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual > PRUs and dual RTUs > * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and > up to two DPI interfaces. > * Integrated Ethernet switch supporting up to a total of 8 external ports in > addition to legacy Ethernet switch of up to 2 ports. > * System MMU (SMMU) Version 3.0 and advanced virtualisation > capabilities. > * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, > 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, > I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > * Configurable L3 Cache and IO-coherent architecture with high data throughput > capable distributed DMA architecture under NAVSS > * Centralized System Controller for Security, Power, and Resource > Management (DMSC) > > See J721E Technical Reference Manual (SPRUIL1, May 2019) > for further details: http://www.ti.com/lit/pdf/spruil1 > > Signed-off-by: Nishanth Menon <nm@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ > 1 file changed, 3 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
On 10:45-20190614, Rob Herring wrote: > On Wed, May 22, 2019 at 11:19:16AM -0500, Nishanth Menon wrote: > > The J721E SoC belongs to the K3 Multicore SoC architecture platform, > > providing advanced system integration to enable lower system costs > > of automotive applications such as infotainment, cluster, premium > > Audio, Gateway, industrial and a range of broad market applications. > > This SoC is designed around reducing the system cost by eliminating > > the need of an external system MCU and is targeted towards ASIL-B/C > > certification/requirements in addition to allowing complex software > > and system use-cases. > > > > Some highlights of this SoC are: > > * Dual Cortex-A72s in a single cluster, three clusters of lockstep > > capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), > > C7x floating point Vector DSP, Two C66x floating point DSPs. > > * 3D GPU PowerVR Rogue 8XE GE8430 > > * Vision Processing Accelerator (VPAC) with image signal processor and Depth > > and Motion Processing Accelerator (DMPAC) > > * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual > > PRUs and dual RTUs > > * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and > > up to two DPI interfaces. > > * Integrated Ethernet switch supporting up to a total of 8 external ports in > > addition to legacy Ethernet switch of up to 2 ports. > > * System MMU (SMMU) Version 3.0 and advanced virtualisation > > capabilities. > > * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, > > 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, > > I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > > * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > > management. > > * Configurable L3 Cache and IO-coherent architecture with high data throughput > > capable distributed DMA architecture under NAVSS > > * Centralized System Controller for Security, Power, and Resource > > Management (DMSC) > > > > See J721E Technical Reference Manual (SPRUIL1, May 2019) > > for further details: http://www.ti.com/lit/pdf/spruil1 > > > > Signed-off-by: Nishanth Menon <nm@ti.com> > > --- > > Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > Okay for now, but please convert K3 and other TI SoCs to schema soon. > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks Rob. Will do the change to rst soon (hopefully post in the 5.3 window).
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt index 6a059cabb2da..333e7256126a 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.txt +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt @@ -13,6 +13,9 @@ architecture it uses, using one of the following compatible values: - AM654 compatible = "ti,am654"; +- J721E + compatible = "ti,j721e"; + Boards ------
The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> --- Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ 1 file changed, 3 insertions(+)