| Message ID | 20190618125433.9739-5-andrew.murray@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: save/restore ETMv4 context across CPU low power states | expand |
On 18/06/2019 13:54, Andrew Murray wrote: > To improve clarity, let's update the comment for etm4_os_unlock > to use the name of the register as per the ETM architecture > specification. nit: It also "fixes" the comment. Writing any value doesn't unlock the trace unit. It must be "0". > > Signed-off-by: Andrew Murray <andrew.murray@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 885c4f2c691c..bda90d4cd62b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -47,7 +47,7 @@ static enum cpuhp_state hp_online; > > static void etm4_os_unlock(struct etmv4_drvdata *drvdata) > { > - /* Writing any value to ETMOSLAR unlocks the trace registers */ > + /* Writing 0 to TRCOSLAR unlocks the trace registers */ > writel_relaxed(0x0, drvdata->base + TRCOSLAR); > drvdata->os_unlock = true; > isb(); With the above : Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
On Wed, Jun 19, 2019 at 11:46:07AM +0100, Suzuki K Poulose wrote: > > > On 18/06/2019 13:54, Andrew Murray wrote: > > To improve clarity, let's update the comment for etm4_os_unlock > > to use the name of the register as per the ETM architecture > > specification. > > nit: It also "fixes" the comment. Writing any value doesn't unlock > the trace unit. It must be "0". > > > > > Signed-off-by: Andrew Murray <andrew.murray@arm.com> > > --- > > drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > > index 885c4f2c691c..bda90d4cd62b 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > > @@ -47,7 +47,7 @@ static enum cpuhp_state hp_online; > > static void etm4_os_unlock(struct etmv4_drvdata *drvdata) > > { > > - /* Writing any value to ETMOSLAR unlocks the trace registers */ > > + /* Writing 0 to TRCOSLAR unlocks the trace registers */ > > writel_relaxed(0x0, drvdata->base + TRCOSLAR); > > drvdata->os_unlock = true; > > isb(); > > With the above : > > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Thanks, I'll update the message. Andrew Murray
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 885c4f2c691c..bda90d4cd62b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -47,7 +47,7 @@ static enum cpuhp_state hp_online; static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { - /* Writing any value to ETMOSLAR unlocks the trace registers */ + /* Writing 0 to TRCOSLAR unlocks the trace registers */ writel_relaxed(0x0, drvdata->base + TRCOSLAR); drvdata->os_unlock = true; isb();
To improve clarity, let's update the comment for etm4_os_unlock to use the name of the register as per the ETM architecture specification. Signed-off-by: Andrew Murray <andrew.murray@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)