| Message ID | 20190716115745.12585-26-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ram: rk3399: Add LPDDR4 support | expand |
On 2019/7/16 下午7:57, Jagan Teki wrote: > It is possible in lpddr4 dram, where both the channels would > start at same time with ZQ Cal Start. If it uses ZQ Call start > then it will use RZQ. > > For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe > connect to both channel. If ZQ Cal Start at the same time, > it will use the same RZQ. > > It is not a problem of using RZQ in both the channels, but can not > use at the same time. > > So, to avoid this, we have an option of dram tINIT3 value for > increasing the frequency for channel 1. > > This patch increase the available tINIT3 with existing running > dram frequency. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 023838a301..beb4f6de54 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, > sizeof(struct rk3399_ddr_pctl_regs) - 4); > writel(params_ctl[0], &denali_ctl[0]); > > + /* > + * two channel init at the same time, then ZQ Cal Start > + * at the same time, it will use the same RZQ, but cannot > + * start at the same time. > + * > + * So, increase tINIT3 for channel 1, will avoid two > + * channel ZQ Cal Start at the same time > + */ > + if (params->base.dramtype == LPDDR4 && channel == 1) { > + tmp = ((params->base.ddr_freq * MHz + 999) / 1000); > + tmp1 = readl(&denali_ctl[14]); > + writel(tmp + tmp1, &denali_ctl[14]); > + } > + > copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], > sizeof(struct rk3399_ddr_pi_regs)); >
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 023838a301..beb4f6de54 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); + /* + * two channel init at the same time, then ZQ Cal Start + * at the same time, it will use the same RZQ, but cannot + * start at the same time. + * + * So, increase tINIT3 for channel 1, will avoid two + * channel ZQ Cal Start at the same time + */ + if (params->base.dramtype == LPDDR4 && channel == 1) { + tmp = ((params->base.ddr_freq * MHz + 999) / 1000); + tmp1 = readl(&denali_ctl[14]); + writel(tmp + tmp1, &denali_ctl[14]); + } + copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs));