| Message ID | 20190717180624.20354-1-tvrtko.ursulin@linux.intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | MCR fixes and more | expand |
On 17/07/2019 20:18, Patchwork wrote: > == Series Details == > > Series: MCR fixes and more > URL : https://patchwork.freedesktop.org/series/63831/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6502 -> Patchwork_13676 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13676/ > > Known issues > ------------ > > Here are the changes found in Patchwork_13676 that come from known issues: > > ### IGT changes ### > > #### Possible fixes #### > > * igt@gem_basic@bad-close: > - fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6502/fi-icl-u3/igt@gem_basic@bad-close.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13676/fi-icl-u3/igt@gem_basic@bad-close.html > > * igt@gem_ctx_create@basic-files: > - fi-icl-u3: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> [PASS][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6502/fi-icl-u3/igt@gem_ctx_create@basic-files.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13676/fi-icl-u3/igt@gem_ctx_create@basic-files.html > > * {igt@gem_ctx_switch@legacy-render}: > - fi-icl-guc: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6502/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13676/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html > > * {igt@gem_ctx_switch@rcs0}: > - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8] > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6502/fi-icl-u2/igt@gem_ctx_switch@rcs0.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13676/fi-icl-u2/igt@gem_ctx_switch@rcs0.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 > [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 > [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 > > > Participating hosts (52 -> 47) > ------------------------------ > > Additional (1): fi-apl-guc > Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_6502 -> Patchwork_13676 > > CI_DRM_6502: 606a844d5d932fb07b2377b95c0fe7b08383e32a @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_13676: d3068b3ac79ffaaa0ade8d8ef004e1f9fa2b59c6 @ git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > d3068b3ac79f drm/i915/icl: Add Wa_1409178092 > 69c8f4a77a62 drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 > 478276140729 drm/i915: Skip CS verification of L3 bank registers > 05988d2693e3 drm/i915: Fix and improve MCR selection logic > 9874e34931ae drm/i915: Trust programmed MCR in read_subslice_reg > 53048f39ddd0 drm/i915: Fix GEN8_MCR_SELECTOR programming Pushed since it fixes some obvious problem, even if it doesn't answer all the questions. Regards, Tvrtko
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A few bugs in programming the MCR register sneaked in past code review. First of all fls() usage is wrong and suffers from off-by-one problem. Secondly the assert in WaProgramMgsrForL3BankSpecificMmioReads is also wrong due inverted logic. With MCR programming fixed we can stop ignoring the engine workarounds verification of GEN8_L3SQCREG4. But not registers in the 0xb100-0xb3ff range which cannot be read reliably by the command streamers. The logic is also improved to not only assert when static MCR configuration would not work given specific subslice and L3 bank configuration, but to find a valid static configuration if possible. Finally there was a missing perfomance based workaround which loosely belongs to this overall story of ICL, subslices, L3 banks and workarounds. Tvrtko Ursulin (6): drm/i915: Fix GEN8_MCR_SELECTOR programming drm/i915: Trust programmed MCR in read_subslice_reg drm/i915: Fix and improve MCR selection logic drm/i915: Skip CS verification of L3 bank registers drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 drm/i915/icl: Add Wa_1409178092 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 56 ++----- drivers/gpu/drm/i915/gt/intel_workarounds.c | 161 ++++++++++++-------- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/i915_reg.h | 3 + 4 files changed, 109 insertions(+), 113 deletions(-)