| Message ID | 1562235864-12953-1-git-send-email-abel.vesa@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq: Default parents for PCIE1 clocks | expand |
On Thu, Jul 04, 2019 at 01:24:24PM +0300, Abel Vesa wrote: > Set default parents for PCIE1_CTRL and PCIE1_PHY clocks. Can you add a few words about why this change is necessary? Shawn > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > index e3df9b8..23bf85f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts > @@ -235,6 +235,10 @@ > <&clk IMX8MQ_CLK_PCIE1_PHY>, > <&pcie0_refclk>; > clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, > + <&clk IMX8MQ_CLK_PCIE1_PHY>; > + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, > + <&clk IMX8MQ_SYS2_PLL_100M>; > status = "okay"; > }; > > -- > 2.7.4 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e3df9b8..23bf85f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -235,6 +235,10 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>; status = "okay"; };
Set default parents for PCIE1_CTRL and PCIE1_PHY clocks. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++ 1 file changed, 4 insertions(+)