| Message ID | 20190704090205.19400-2-fe@dev.tdt.de (mailing list archive) |
|---|---|
| State | Rejected, archived |
| Headers | show |
| Series | Update pcengines-apuv2 platform device | expand |
On 04.07.19 11:02, Florian Eckert wrote: > On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset > the ports from the userspace, add the definition to this platform > device. The gpio can then be exported by the legancy gpio subsystem to > toggle the mpcie reset pin. Are you sure they're also available on APUv2 (not just v3) ? --mtx
On 2019-07-08 21:44, Enrico Weigelt, metux IT consult wrote: > On 04.07.19 11:02, Florian Eckert wrote: >> On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to >> reset >> the ports from the userspace, add the definition to this platform >> device. The gpio can then be exported by the legancy gpio subsystem to >> toggle the mpcie reset pin. > > Are you sure they're also available on APUv2 (not just v3) ? We have the following models on APU2 family: The schematic could be downloaded for all APU2 family boards from this side. See https://www.pcengines.ch/apu2.htm They all use the similar PCB with some minimal changes. APU2 2 mpcie slot apu2d0 (2 GB DRAM, 2 i211AT NICs) apu2d2 (2 GB DRAM, 3 i211AT NICs) apu2d4 (4 GB DRAM, 3 i210AT NICs) J14 (USB + SIM1) PE3_RST to GPIO G51 J13 (USB + SIM2) PE4_RST to GPIO G55 APU3 3 mpcie slot apu3c2 (2 GB DRAM, 3 i211AT NICs, optimized for 3G/LTE modems) apu3c4 (4 GB DRAM, 3 i211AT NICs, optimized for 3G/LTE modems) J16 (PCIe + USB no SIM) not connected to a userland GPIO J15 (USB SIM1) PE4_RST to GPIO G55 J14 (mSATA or USB SIM2) PE3_RST to GPIO G51 APU4 3 mpcie slot apu4c2 (2 GB DRAM, 4 i211AT NICs) apu4c4 (4 GB DRAM, 4 i211AT NICs) J15 (PCIe + USB no SIM) not connected to a userland GPIO J14 (USB SIM1) PE4_RST to GPIO G55 J13 (mSATA or USB SIM2) PE3_RST to GPIO G51 Please check again so that I have not done any mistake. So all USB only mpcie slots could be reseted by a GPIO G51 and G55. Kind regards Flo
On 04.07.19 11:02, Florian Eckert wrote: > On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset > the ports from the userspace, add the definition to this platform > device. The gpio can then be exported by the legancy gpio subsystem to > toggle the mpcie reset pin. > Just tested your patch on an apu3. The driver itself seems to work, but the pins don't seem to actually do anything. How exactly did you test it ? Do you have some test case ? --mtx
>> On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to >> reset >> the ports from the userspace, add the definition to this platform >> device. The gpio can then be exported by the legancy gpio subsystem to >> toggle the mpcie reset pin. >> > > Just tested your patch on an apu3. The driver itself seems to work, > but the pins don't seem to actually do anything. > > How exactly did you test it ? Do you have some test case ? I plugged in a mpcie usb modem. In my test case it was a EC25 from Quectel in mpcie2 port. After that I did a reboot and exported the gpio via "/sys/class/gpio" Then I executed the command "echo 0 > /sys/class/gpio/<name>/value" and "echo 1 > /sys/class/gpio/<name>/value". Then I have seen the log message in the kernel that the device did an unregistration/registration . -- Florian
On 15.07.19 16:38, Florian Eckert wrote: > I plugged in a mpcie usb modem. > In my test case it was a EC25 from Quectel in mpcie2 port. > After that I did a reboot and exported the gpio via "/sys/class/gpio" > Then I executed the command "echo 0 > /sys/class/gpio/<name>/value" and > "echo 1 > /sys/class/gpio/<name>/value". > Then I have seen the log message in the kernel that the device did an > unregistration/registration hmm, did the same, tried both gpios (mpcie2_reset, mpcie3_reset), but nothin happened. But strange: I'm missing some hw, modem doesn't appear ... I'll have to check again whether i've got unstable hw or missing some kernel config. --mtx
On 04.07.19 11:02, Florian Eckert wrote: > On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset > the ports from the userspace, add the definition to this platform > device. The gpio can then be exported by the legancy gpio subsystem to > toggle the mpcie reset pin. > > Signed-off-by: Florian Eckert <fe@dev.tdt.de> > --- > drivers/platform/x86/pcengines-apuv2.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/platform/x86/pcengines-apuv2.c b/drivers/platform/x86/pcengines-apuv2.c > index c1ca931e1fab..f6d8ed100cab 100644 > --- a/drivers/platform/x86/pcengines-apuv2.c > +++ b/drivers/platform/x86/pcengines-apuv2.c > @@ -32,6 +32,8 @@ > #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1 > #define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1 > #define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2 > +#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO59_DEVSLP0 > +#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51 > > /* order in which the gpio lines are defined in the register list */ > #define APU2_GPIO_LINE_LED1 0 > @@ -39,6 +41,8 @@ > #define APU2_GPIO_LINE_LED3 2 > #define APU2_GPIO_LINE_MODESW 3 > #define APU2_GPIO_LINE_SIMSWAP 4 > +#define APU2_GPIO_LINE_MPCIE2 5 > +#define APU2_GPIO_LINE_MPCIE3 6 > > /* gpio device */ > > @@ -48,6 +52,8 @@ static int apu2_gpio_regs[] = { > [APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3, > [APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW, > [APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP, > + [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2, > + [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3, > }; > > static const char * const apu2_gpio_names[] = { > @@ -56,6 +62,8 @@ static const char * const apu2_gpio_names[] = { > [APU2_GPIO_LINE_LED3] = "front-led3", > [APU2_GPIO_LINE_MODESW] = "front-button", > [APU2_GPIO_LINE_SIMSWAP] = "simswap", > + [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset", > + [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset", > }; > > static const struct amd_fch_gpio_pdata board_apu2 = { > Acked-by: Enrico Weigelt <info@metux.net> But note that these gpio's later will be bound to an appropriate driver. I've got a patch in the queue that uses LED subsystem, but haven't sorted out whether it's better to go via reset subsystem (and add a gpio-based reset driver first). --mtx
diff --git a/drivers/platform/x86/pcengines-apuv2.c b/drivers/platform/x86/pcengines-apuv2.c index c1ca931e1fab..f6d8ed100cab 100644 --- a/drivers/platform/x86/pcengines-apuv2.c +++ b/drivers/platform/x86/pcengines-apuv2.c @@ -32,6 +32,8 @@ #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1 #define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1 #define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2 +#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO59_DEVSLP0 +#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51 /* order in which the gpio lines are defined in the register list */ #define APU2_GPIO_LINE_LED1 0 @@ -39,6 +41,8 @@ #define APU2_GPIO_LINE_LED3 2 #define APU2_GPIO_LINE_MODESW 3 #define APU2_GPIO_LINE_SIMSWAP 4 +#define APU2_GPIO_LINE_MPCIE2 5 +#define APU2_GPIO_LINE_MPCIE3 6 /* gpio device */ @@ -48,6 +52,8 @@ static int apu2_gpio_regs[] = { [APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3, [APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW, [APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP, + [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2, + [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3, }; static const char * const apu2_gpio_names[] = { @@ -56,6 +62,8 @@ static const char * const apu2_gpio_names[] = { [APU2_GPIO_LINE_LED3] = "front-led3", [APU2_GPIO_LINE_MODESW] = "front-button", [APU2_GPIO_LINE_SIMSWAP] = "simswap", + [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset", + [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset", }; static const struct amd_fch_gpio_pdata board_apu2 = {
On APUx we have also mpcie2/mpcie3 reset pins. To make it possible to reset the ports from the userspace, add the definition to this platform device. The gpio can then be exported by the legancy gpio subsystem to toggle the mpcie reset pin. Signed-off-by: Florian Eckert <fe@dev.tdt.de> --- drivers/platform/x86/pcengines-apuv2.c | 8 ++++++++ 1 file changed, 8 insertions(+)