| Message ID | 20190717023951.5064-1-ben.chuang@genesyslogic.com.tw (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] mmc: sdhci: Add PLL Enable support to internal clock setup | expand |
On Wed, 17 Jul 2019 at 04:39, Ben Chuang <ben.chuang@genesyslogic.com.tw> wrote: > > The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable > setup as part of the internal clock setup as described in 3.2.1 Internal > Clock Setup Sequence of SD Host Controller Simplified Specification > Version 4.20. This changes the timeouts to the new specification of > 150ms for each step and is documented as safe for "prior versions which > do not support PLL Enable." > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Co-developed-by: Michael K Johnson <johnsonm@danlj.org> > Signed-off-by: Michael K Johnson <johnsonm@danlj.org> > --- > drivers/mmc/host/sdhci.c | 33 ++++++++++++++++++++++++--------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 59acf8e3331e..fd684d7a5f15 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1636,15 +1636,11 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) > clk |= SDHCI_CLOCK_INT_EN; > sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > > - /* Wait max 20 ms */ > - timeout = ktime_add_ms(ktime_get(), 20); > - while (1) { > - bool timedout = ktime_after(ktime_get(), timeout); > - > - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > - if (clk & SDHCI_CLOCK_INT_STABLE) > - break; > - if (timedout) { > + /* Wait max 150 ms */ > + timeout = ktime_add_ms(ktime_get(), 150); > + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) > + & SDHCI_CLOCK_INT_STABLE)) { > + if (ktime_after(ktime_get(), timeout)) { > pr_err("%s: Internal clock never stabilised.\n", > mmc_hostname(host->mmc)); > sdhci_dumpregs(host); > @@ -1653,8 +1649,27 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) > udelay(10); This looks like it could be changed to an usleep_range(), perhaps an additional change on top? > } > > + clk |= SDHCI_CLOCK_PLL_EN; > + clk &= ~SDHCI_CLOCK_INT_STABLE; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + /* Wait max 150 ms */ > + timeout = ktime_add_ms(ktime_get(), 150); > + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) > + & SDHCI_CLOCK_INT_STABLE)) { > + if (ktime_after(ktime_get(), timeout)) { > + pr_err("%s: PLL clock never stabilised.\n", > + mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return; > + } > + udelay(10); Ditto. > + } > + > clk |= SDHCI_CLOCK_CARD_EN; > sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + mdelay(1); This is new, maybe add a comment and change to usleep_range(). > } > EXPORT_SYMBOL_GPL(sdhci_enable_clk); > > -- > 2.22.0 > > ________________________________ > > Genesys Logic Email Confidentiality Notice: > This mail and any attachments may contain information that is confidential, proprietary, privileged or otherwise protected by law. The mail is intended solely for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this mail, you are not authorized to read, print, copy or disseminate this mail. > > If you have received this email in error, please notify us immediately by reply email and immediately delete this message and any attachments from your system. Please be noted that any unauthorized use, dissemination, distribution or copying of this email is strictly prohibited. > ________________________________ If you want me to apply the patch, you have to drop the above notice. Kind regards Uffe
On Wed, Jul 24, 2019 at 09:19:30AM +0200, Ulf Hansson wrote: > > Genesys Logic Email Confidentiality Notice: > > This mail and any attachments may contain information that is confidential, proprietary, privileged or otherwise protected by law. The mail is intended solely for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this mail, you are not authorized to read, print, copy or disseminate this mail. > > > > If you have received this email in error, please notify us immediately by reply email and immediately delete this message and any attachments from your system. Please be noted that any unauthorized use, dissemination, distribution or copying of this email is strictly prohibited. > > ________________________________ > > If you want me to apply the patch, you have to drop the above notice. Ben is the primary author and can respond on the requested code changes; I helped break the work apart into the two patches and did small changes to improve the code. Ben's SMTP server at Genesys auto-appends the confidentiality notice without giving him the opportunity to control it. I have the patch set co-developed in a shared Git repository without the automated email addition ever applied, so when Ben works out the substantial changes, I can send final patches to the list without the mail-mangling robot getting in the way. He'll still be the primary author.
(Working around Ben's SMTP server noise, responding on his behalf...) On Wed, Jul 24, 2019 at 09:19:30AM +0200, Ulf Hansson wrote: > This looks like it could be changed to an usleep_range(), perhaps an > additional change on top? ... > Ditto. In both cases yes, changed. > > + mdelay(1); > > This is new, maybe add a comment and change to usleep_range(). Entirely removed. New patch attached for any further review, I can re-send the patchset properly without the notice for merge when you're happy with it. The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. This changes the timeouts to the new specification of 150ms for each step and is documented as safe for "prior versions which do not support PLL Enable." Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..14957578bf2e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); while (1) { bool timedout = ktime_after(ktime_get(), timeout); @@ -1650,7 +1650,28 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) sdhci_dumpregs(host); return; } - udelay(10); + usleep_range(10,15); + } + + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + usleep_range(10,15); } clk |= SDHCI_CLOCK_CARD_EN; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001
On Thu, 25 Jul 2019 at 13:15, Michael K. Johnson <johnsonm@danlj.org> wrote: > > (Working around Ben's SMTP server noise, responding on his behalf...) > > On Wed, Jul 24, 2019 at 09:19:30AM +0200, Ulf Hansson wrote: > > This looks like it could be changed to an usleep_range(), perhaps an > > additional change on top? > ... > > Ditto. > > In both cases yes, changed. > > > > + mdelay(1); > > > > This is new, maybe add a comment and change to usleep_range(). > > Entirely removed. > > New patch attached for any further review, I can re-send the patchset > properly without the notice for merge when you're happy with it. I need an ack from Adrian, but it's probably best to resend anyway. Kind regards Uffe > > > The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable > setup as part of the internal clock setup as described in 3.2.1 Internal > Clock Setup Sequence of SD Host Controller Simplified Specification > Version 4.20. This changes the timeouts to the new specification of > 150ms for each step and is documented as safe for "prior versions which > do not support PLL Enable." > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Co-developed-by: Michael K Johnson <johnsonm@danlj.org> > Signed-off-by: Michael K Johnson <johnsonm@danlj.org> > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 59acf8e3331e..14957578bf2e 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) > clk |= SDHCI_CLOCK_INT_EN; > sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > > - /* Wait max 20 ms */ > - timeout = ktime_add_ms(ktime_get(), 20); > + /* Wait max 150 ms */ > + timeout = ktime_add_ms(ktime_get(), 150); > while (1) { > bool timedout = ktime_after(ktime_get(), timeout); > > @@ -1650,7 +1650,28 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) > sdhci_dumpregs(host); > return; > } > - udelay(10); > + usleep_range(10,15); > + } > + > + clk |= SDHCI_CLOCK_PLL_EN; > + clk &= ~SDHCI_CLOCK_INT_STABLE; > + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); > + > + /* Wait max 150 ms */ > + timeout = ktime_add_ms(ktime_get(), 150); > + while (1) { > + bool timedout = ktime_after(ktime_get(), timeout); > + > + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); > + if (clk & SDHCI_CLOCK_INT_STABLE) > + break; > + if (timedout) { > + pr_err("%s: PLL clock never stabilised.\n", > + mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return; > + } > + usleep_range(10,15); > } > > clk |= SDHCI_CLOCK_CARD_EN; > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > index 199712e7adbb..72601a4d2e95 100644 > --- a/drivers/mmc/host/sdhci.h > +++ b/drivers/mmc/host/sdhci.h > @@ -114,6 +114,7 @@ > #define SDHCI_DIV_HI_MASK 0x300 > #define SDHCI_PROG_CLOCK_MODE 0x0020 > #define SDHCI_CLOCK_CARD_EN 0x0004 > +#define SDHCI_CLOCK_PLL_EN 0x0008 > #define SDHCI_CLOCK_INT_STABLE 0x0002 > #define SDHCI_CLOCK_INT_EN 0x0001 >
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..fd684d7a5f15 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,15 +1636,11 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); - while (1) { - bool timedout = ktime_after(ktime_get(), timeout); - - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - if (clk & SDHCI_CLOCK_INT_STABLE) - break; - if (timedout) { + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); @@ -1653,8 +1649,27 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + mdelay(1); } EXPORT_SYMBOL_GPL(sdhci_enable_clk);