| Message ID | 93df6e7d81a404a43af684e2f96bdb6561ed87fe.1563971855.git.leonard.crestez@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PM / devfreq: Add imx driver | expand |
Hi, 2019년 7월 24일 (수) 오후 10:36, Leonard Crestez <leonard.crestez@nxp.com>님이 작성: > > Add initial dt bindings for the interconnects inside i.MX chips. > Multiple external IPs are involved but SOC integration means the > software controllable interfaces are very similar. > > This is initially only for imx8mm but add an "fsl,imx-bus" fallback > similar to exynos-bus. > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > --- > .../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml > > diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml > new file mode 100644 > index 000000000000..87f90cddfd29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/devfreq/imx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Generic i.MX bus frequency device > + > +maintainers: > + - Leonard Crestez <leonard.crestez@nxp.com> > + > +description: | > + The i.MX SoC family has multiple buses for which clock frequency (and sometimes > + voltage) can be adjusted. > + > + Some of those buses expose register areas mentioned in the memory maps as GPV > + ("Global Programmers View") but not all. Access to this area might be denied for > + normal world. > + > + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris > + FlexNOC but DT bindings are specific to the integration of these bus > + interconnect IPs into imx SOCs. > + > +properties: > + reg: > + maxItems: 1 > + description: GPV area > + > + compatible: > + contains: > + enum: > + - fsl,imx8m-noc > + - fsl,imx8m-nic > + - fsl,imx8m-ddrc > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - clocks > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mm-clock.h> > + ddrc: dram-controller@3d400000 { > + compatible = "fsl,imx8mm-ddrc"; s/imx8mm/imx8m > + reg = <0x3d400000 0x400000>; > + clocks = <&clk IMX8MM_CLK_DRAM>; > + operating-points-v2 = <&ddrc_opp_table>; > + }; > + > + - | > + noc: noc@32700000 { > + compatible = "fsl,imx8mm-noc"; s/imx8mm/imx8m > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MM_CLK_NOC>; > + operating-points-v2 = <&noc_opp_table>; > + }; > -- > 2.17.1 >
diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml new file mode 100644 index 000000000000..87f90cddfd29 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/imx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and sometimes + voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied for + normal world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris + FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + reg: + maxItems: 1 + description: GPV area + + compatible: + contains: + enum: + - fsl,imx8m-noc + - fsl,imx8m-nic + - fsl,imx8m-ddrc + + clocks: + maxItems: 1 + +required: + - compatible + - clocks + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc"; + reg = <0x3d400000 0x400000>; + clocks = <&clk IMX8MM_CLK_DRAM>; + operating-points-v2 = <&ddrc_opp_table>; + }; + + - | + noc: noc@32700000 { + compatible = "fsl,imx8mm-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + operating-points-v2 = <&noc_opp_table>; + };
Add initial dt bindings for the interconnects inside i.MX chips. Multiple external IPs are involved but SOC integration means the software controllable interfaces are very similar. This is initially only for imx8mm but add an "fsl,imx-bus" fallback similar to exynos-bus. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> --- .../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml