| Message ID | 20190717080621.40424-5-yanaijie@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | implement KASLR for powerpc/fsl_booke/32 | expand |
Le 17/07/2019 à 10:06, Jason Yan a écrit : > Add a new helper create_tlb_entry() to create a tlb entry by the virtual > and physical address. This is a preparation to support boot kernel at a > randomized address. > > Signed-off-by: Jason Yan <yanaijie@huawei.com> > Cc: Diana Craciun <diana.craciun@nxp.com> > Cc: Michael Ellerman <mpe@ellerman.id.au> > Cc: Christophe Leroy <christophe.leroy@c-s.fr> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> > Cc: Paul Mackerras <paulus@samba.org> > Cc: Nicholas Piggin <npiggin@gmail.com> > Cc: Kees Cook <keescook@chromium.org> > --- > arch/powerpc/kernel/head_fsl_booke.S | 30 ++++++++++++++++++++++++++++ > arch/powerpc/mm/mmu_decl.h | 1 + > 2 files changed, 31 insertions(+) > > diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S > index adf0505dbe02..a57d44638031 100644 > --- a/arch/powerpc/kernel/head_fsl_booke.S > +++ b/arch/powerpc/kernel/head_fsl_booke.S > @@ -1114,6 +1114,36 @@ __secondary_hold_acknowledge: > .long -1 > #endif > > +/* > + * Create a 64M tlb by address and entry > + * r3/r4 - physical address > + * r5 - virtual address > + * r6 - entry > + */ > +_GLOBAL(create_tlb_entry) > + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ > + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ > + mtspr SPRN_MAS0,r7 /* Write MAS0 */ > + > + lis r6,(MAS1_VALID|MAS1_IPROT)@h > + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l > + mtspr SPRN_MAS1,r6 /* Write MAS1 */ > + > + lis r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h > + ori r6,r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l > + and r6,r6,r5 > + ori r6,r6,MAS2_M@l > + mtspr SPRN_MAS2,r6 /* Write MAS2(EPN) */ > + > + mr r8,r4 > + ori r8,r8,(MAS3_SW|MAS3_SR|MAS3_SX) Could drop the mr r8, r4 and do: ori r8,r4,(MAS3_SW|MAS3_SR|MAS3_SX) > + mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ > + > + tlbwe /* Write TLB */ > + isync > + sync > + blr > + > /* > * Create a tlb entry with the same effective and physical address as > * the tlb entry used by the current running code. But set the TS to 1. > diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h > index 32c1a191c28a..d7737cf97cee 100644 > --- a/arch/powerpc/mm/mmu_decl.h > +++ b/arch/powerpc/mm/mmu_decl.h > @@ -142,6 +142,7 @@ extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, > extern void adjust_total_lowmem(void); > extern int switch_to_as1(void); > extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu); > +extern void create_tlb_entry(phys_addr_t phys, unsigned long virt, int entry); Please please do not add new declarations with the useless 'extern' keyword. See checkpatch report: https://openpower.xyz/job/snowpatch/job/snowpatch-linux-checkpatch/8124//artifact/linux/checkpatch.log > #endif > extern void loadcam_entry(unsigned int index); > extern void loadcam_multi(int first_idx, int num, int tmp_idx); >
On 2019/7/29 19:05, Christophe Leroy wrote: > > > Le 17/07/2019 à 10:06, Jason Yan a écrit : >> Add a new helper create_tlb_entry() to create a tlb entry by the virtual >> and physical address. This is a preparation to support boot kernel at a >> randomized address. >> >> Signed-off-by: Jason Yan <yanaijie@huawei.com> >> Cc: Diana Craciun <diana.craciun@nxp.com> >> Cc: Michael Ellerman <mpe@ellerman.id.au> >> Cc: Christophe Leroy <christophe.leroy@c-s.fr> >> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> >> Cc: Paul Mackerras <paulus@samba.org> >> Cc: Nicholas Piggin <npiggin@gmail.com> >> Cc: Kees Cook <keescook@chromium.org> >> --- >> arch/powerpc/kernel/head_fsl_booke.S | 30 ++++++++++++++++++++++++++++ >> arch/powerpc/mm/mmu_decl.h | 1 + >> 2 files changed, 31 insertions(+) >> >> diff --git a/arch/powerpc/kernel/head_fsl_booke.S >> b/arch/powerpc/kernel/head_fsl_booke.S >> index adf0505dbe02..a57d44638031 100644 >> --- a/arch/powerpc/kernel/head_fsl_booke.S >> +++ b/arch/powerpc/kernel/head_fsl_booke.S >> @@ -1114,6 +1114,36 @@ __secondary_hold_acknowledge: >> .long -1 >> #endif >> +/* >> + * Create a 64M tlb by address and entry >> + * r3/r4 - physical address >> + * r5 - virtual address >> + * r6 - entry >> + */ >> +_GLOBAL(create_tlb_entry) >> + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ >> + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ >> + mtspr SPRN_MAS0,r7 /* Write MAS0 */ >> + >> + lis r6,(MAS1_VALID|MAS1_IPROT)@h >> + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l >> + mtspr SPRN_MAS1,r6 /* Write MAS1 */ >> + >> + lis r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h >> + ori r6,r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l >> + and r6,r6,r5 >> + ori r6,r6,MAS2_M@l >> + mtspr SPRN_MAS2,r6 /* Write MAS2(EPN) */ >> + >> + mr r8,r4 >> + ori r8,r8,(MAS3_SW|MAS3_SR|MAS3_SX) > > Could drop the mr r8, r4 and do: > > ori r8,r4,(MAS3_SW|MAS3_SR|MAS3_SX) > OK, thanks for the suggestion. >> + mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ >> + >> + tlbwe /* Write TLB */ >> + isync >> + sync >> + blr >> + >> /* >> * Create a tlb entry with the same effective and physical address as >> * the tlb entry used by the current running code. But set the TS to 1. >> diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h >> index 32c1a191c28a..d7737cf97cee 100644 >> --- a/arch/powerpc/mm/mmu_decl.h >> +++ b/arch/powerpc/mm/mmu_decl.h >> @@ -142,6 +142,7 @@ extern unsigned long calc_cam_sz(unsigned long >> ram, unsigned long virt, >> extern void adjust_total_lowmem(void); >> extern int switch_to_as1(void); >> extern void restore_to_as0(int esel, int offset, void *dt_ptr, int >> bootcpu); >> +extern void create_tlb_entry(phys_addr_t phys, unsigned long virt, >> int entry); > > Please please do not add new declarations with the useless 'extern' > keyword. See checkpatch report: > https://openpower.xyz/job/snowpatch/job/snowpatch-linux-checkpatch/8124//artifact/linux/checkpatch.log > Will drop all useless 'extern' in this and other patches, thanks. > >> #endif >> extern void loadcam_entry(unsigned int index); >> extern void loadcam_multi(int first_idx, int num, int tmp_idx); >> > > . >
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index adf0505dbe02..a57d44638031 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -1114,6 +1114,36 @@ __secondary_hold_acknowledge: .long -1 #endif +/* + * Create a 64M tlb by address and entry + * r3/r4 - physical address + * r5 - virtual address + * r6 - entry + */ +_GLOBAL(create_tlb_entry) + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ + mtspr SPRN_MAS0,r7 /* Write MAS0 */ + + lis r6,(MAS1_VALID|MAS1_IPROT)@h + ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l + mtspr SPRN_MAS1,r6 /* Write MAS1 */ + + lis r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h + ori r6,r6,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l + and r6,r6,r5 + ori r6,r6,MAS2_M@l + mtspr SPRN_MAS2,r6 /* Write MAS2(EPN) */ + + mr r8,r4 + ori r8,r8,(MAS3_SW|MAS3_SR|MAS3_SX) + mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ + + tlbwe /* Write TLB */ + isync + sync + blr + /* * Create a tlb entry with the same effective and physical address as * the tlb entry used by the current running code. But set the TS to 1. diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index 32c1a191c28a..d7737cf97cee 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h @@ -142,6 +142,7 @@ extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, extern void adjust_total_lowmem(void); extern int switch_to_as1(void); extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu); +extern void create_tlb_entry(phys_addr_t phys, unsigned long virt, int entry); #endif extern void loadcam_entry(unsigned int index); extern void loadcam_multi(int first_idx, int num, int tmp_idx);
Add a new helper create_tlb_entry() to create a tlb entry by the virtual and physical address. This is a preparation to support boot kernel at a randomized address. Signed-off-by: Jason Yan <yanaijie@huawei.com> Cc: Diana Craciun <diana.craciun@nxp.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Christophe Leroy <christophe.leroy@c-s.fr> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Kees Cook <keescook@chromium.org> --- arch/powerpc/kernel/head_fsl_booke.S | 30 ++++++++++++++++++++++++++++ arch/powerpc/mm/mmu_decl.h | 1 + 2 files changed, 31 insertions(+)