@@ -579,7 +579,7 @@ cases, deviating from) the kernel coding style.
Register macro definition style
-------------------------------
-The style guide for ``i915_reg.h``.
+The style guide for register definitions in header files.
-.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
+.. kernel-doc:: drivers/gpu/drm/i915/i915_reg_types.h
:doc: The i915 register macro definition style guide
@@ -28,6 +28,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_mipi_dsi.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
@@ -34,6 +34,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
@@ -28,6 +28,7 @@
#include <drm/i915_component.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_display_types.h"
#include "intel_lpe_audio.h"
@@ -5,6 +5,7 @@
#include <drm/drm_atomic_state_helper.h>
+#include "i915_reg.h"
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
@@ -22,6 +22,7 @@
*
*/
+#include "i915_reg.h"
#include "intel_color.h"
#include "intel_display_types.h"
@@ -3,6 +3,7 @@
* Copyright © 2018 Intel Corporation
*/
+#include "i915_reg.h"
#include "intel_combo_phy.h"
#include "intel_display_types.h"
@@ -35,6 +35,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_ddi.h"
@@ -6,7 +6,7 @@
#ifndef __INTEL_CRT_H__
#define __INTEL_CRT_H__
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_encoder;
@@ -28,6 +28,7 @@
#include <drm/drm_scdc_helper.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
@@ -57,6 +57,7 @@
#include "display/intel_vdsc.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_acpi.h"
#include "intel_atomic.h"
@@ -10,6 +10,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
#include "intel_csr.h"
@@ -8,7 +8,7 @@
#include "intel_display.h"
#include "intel_runtime_pm.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
struct intel_encoder;
@@ -44,6 +44,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
@@ -10,7 +10,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_connector_state;
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -28,6 +28,7 @@
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
@@ -23,6 +23,7 @@
#include "display/intel_dp.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_sideband.h"
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll_mgr.h"
@@ -4,6 +4,7 @@
*/
#include <drm/drm_mipi_dsi.h>
+#include "i915_reg.h"
#include "intel_dsi.h"
int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
@@ -38,6 +38,7 @@
#include <video/mipi_display.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
@@ -33,6 +33,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_display_types.h"
#include "intel_dvo.h"
@@ -27,7 +27,7 @@
#include <drm/drm_crtc.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct intel_dvo_device {
const char *name;
@@ -41,6 +41,7 @@
#include <drm/drm_fourcc.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
@@ -26,6 +26,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
@@ -35,6 +35,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_gmbus.h"
@@ -41,6 +41,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
@@ -11,7 +11,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_connector;
struct drm_encoder;
@@ -71,6 +71,7 @@
#include <drm/intel_lpe_audio.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_lpe_audio.h"
#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL)
@@ -27,6 +27,7 @@
#include <drm/drm_dp_dual_mode_helper.h>
#include <drm/drm_edid.h>
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_lspcon.h"
@@ -40,6 +40,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
@@ -8,7 +8,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_i915_private;
@@ -35,6 +35,7 @@
#include "display/intel_panel.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_opregion.h"
@@ -39,6 +39,7 @@
#include "intel_dp_aux_backlight.h"
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
+#include "i915_reg.h"
#define CRC_PMIC_PWM_PERIOD_NS 21333
@@ -29,6 +29,7 @@
#include <linux/debugfs.h>
#include <linux/seq_file.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_pipe_crc.h"
@@ -26,6 +26,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -37,6 +37,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
@@ -10,7 +10,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
enum pipe;
@@ -40,6 +40,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_atomic_plane.h"
#include "intel_display_types.h"
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
@@ -36,6 +36,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_display_types.h"
#include "intel_hotplug.h"
@@ -9,6 +9,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_vdsc.h"
@@ -32,6 +32,7 @@
#include <drm/drm_mipi_dsi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
@@ -28,6 +28,7 @@
#include <linux/kernel.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
@@ -74,6 +74,7 @@
#include "i915_gem_context.h"
#include "i915_globals.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -21,6 +21,7 @@
#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
@@ -13,6 +13,7 @@
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vma.h"
@@ -11,6 +11,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gem_stolen.h"
/*
@@ -12,6 +12,7 @@
#include "i915_gem.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
+#include "i915_reg.h"
/**
* DOC: buffer object tiling
@@ -9,6 +9,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_reset.h"
+#include "i915_reg.h"
#include "i915_selftest.h"
#include "gem/selftests/igt_gem_utils.h"
@@ -10,7 +10,7 @@
#include <linux/seqlock.h>
#include "i915_pmu.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "i915_request.h"
#include "i915_selftest.h"
#include "gt/intel_timeline.h"
@@ -27,6 +27,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gt/intel_gt.h"
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_uncore.h"
@@ -7,6 +7,7 @@
#include <linux/sched/clock.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_irq.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
@@ -23,6 +23,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_engine.h"
#include "intel_gt.h"
#include "intel_reset.h"
@@ -137,6 +137,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_engine_pm.h"
@@ -21,6 +21,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_engine.h"
#include "intel_gt.h"
@@ -15,6 +15,7 @@
#include "i915_drv.h"
#include "i915_gpu_error.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
@@ -34,6 +34,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
@@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_context.h"
#include "intel_gt.h"
#include "intel_workarounds.h"
@@ -9,7 +9,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct i915_wa {
i915_reg_t reg;
@@ -12,6 +12,7 @@
#include "gt/intel_gt.h"
#include "intel_guc_fw.h"
#include "i915_drv.h"
+#include "i915_reg.h"
/**
* intel_guc_fw_init_early() - initializes GuC firmware struct
@@ -9,7 +9,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
/* Definitions of GuC H/W registers, bits, etc */
@@ -15,6 +15,7 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
enum {
@@ -6,7 +6,7 @@
#ifndef _INTEL_HUC_H_
#define _INTEL_HUC_H_
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "intel_uc_fw.h"
#include "intel_huc_fw.h"
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "i915_gem_fence_reg.h"
+#include "i915_reg.h"
#include "gvt.h"
static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
@@ -38,6 +38,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#include "trace.h"
#define INVALID_OP (~0U)
@@ -33,6 +33,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
@@ -32,6 +32,7 @@
#include <linux/vfio.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
@@ -33,6 +33,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define GMBUS1_TOTAL_BYTES_SHIFT 16
@@ -37,6 +37,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#include "trace.h"
#if defined(VERBOSE_DEBUG)
@@ -39,6 +39,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
/* XXX FIXME i915 has changed PP_XXX definition */
#define PCH_PP_STATUS _MMIO(0xc7200)
@@ -30,6 +30,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#include "trace.h"
@@ -34,6 +34,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
/**
@@ -34,6 +34,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gt/intel_context.h"
#include "gvt.h"
#include "trace.h"
@@ -40,6 +40,7 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define RING_CTX_OFF(x) \
@@ -28,6 +28,7 @@
#include "gt/intel_engine.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_memcpy.h"
/**
@@ -46,6 +46,7 @@
#include "i915_debugfs.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_csr.h"
#include "intel_pm.h"
@@ -71,6 +71,7 @@
#include "i915_memcpy.h"
#include "i915_perf.h"
#include "i915_query.h"
+#include "i915_reg.h"
#include "i915_suspend.h"
#include "i915_sysfs.h"
#include "i915_trace.h"
@@ -60,7 +60,7 @@
#include "i915_fixed.h"
#include "i915_params.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "i915_utils.h"
#include "display/intel_bios.h"
@@ -55,6 +55,7 @@
#include "gt/intel_workarounds.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -24,6 +24,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_vgpu.h"
@@ -39,6 +39,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -42,6 +42,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gpu_error.h"
#include "i915_memcpy.h"
#include "i915_scatterlist.h"
@@ -49,6 +49,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_pm.h"
@@ -10,7 +10,7 @@
#include <linux/types.h>
#include "display/intel_display.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_crtc;
struct drm_device;
@@ -32,6 +32,7 @@
#include "i915_drv.h"
#include "i915_globals.h"
+#include "i915_reg.h"
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
@@ -200,6 +200,7 @@
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_perf.h"
#include "oa/i915_oa_hsw.h"
#include "oa/i915_oa_bdw.h"
@@ -14,6 +14,7 @@
#include "i915_drv.h"
#include "i915_pmu.h"
+#include "i915_reg.h"
#include "intel_pm.h"
/* Frequency for the sampling timer for events which need it. */
@@ -25,181 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
-#include <linux/bitfield.h>
-#include <linux/bits.h>
-
-/**
- * DOC: The i915 register macro definition style guide
- *
- * Follow the style described here for new macros, and while changing existing
- * macros. Do **not** mass change existing definitions just to update the style.
- *
- * Layout
- * ~~~~~~
- *
- * Keep helper macros near the top. For example, _PIPE() and friends.
- *
- * Prefix macros that generally should not be used outside of this file with
- * underscore '_'. For example, _PIPE() and friends, single instances of
- * registers that are defined solely for the use by function-like macros.
- *
- * Avoid using the underscore prefixed macros outside of this file. There are
- * exceptions, but keep them to a minimum.
- *
- * There are two basic types of register definitions: Single registers and
- * register groups. Register groups are registers which have two or more
- * instances, for example one per pipe, port, transcoder, etc. Register groups
- * should be defined using function-like macros.
- *
- * For single registers, define the register offset first, followed by register
- * contents.
- *
- * For register groups, define the register instance offsets first, prefixed
- * with underscore, followed by a function-like macro choosing the right
- * instance based on the parameter, followed by register contents.
- *
- * Define the register contents (i.e. bit and bit field macros) from most
- * significant to least significant bit. Indent the register content macros
- * using two extra spaces between ``#define`` and the macro name.
- *
- * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
- * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
- * shifted in place, so they can be directly OR'd together. For convenience,
- * function-like macros may be used to define bit fields, but do note that the
- * macros may be needed to read as well as write the register contents.
- *
- * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
- *
- * Group the register and its contents together without blank lines, separate
- * from other registers and their contents with one blank line.
- *
- * Indent macro values from macro names using TABs. Align values vertically. Use
- * braces in macro values as needed to avoid unintended precedence after macro
- * substitution. Use spaces in macro values according to kernel coding
- * style. Use lower case in hexadecimal values.
- *
- * Naming
- * ~~~~~~
- *
- * Try to name registers according to the specs. If the register name changes in
- * the specs from platform to another, stick to the original name.
- *
- * Try to re-use existing register macro definitions. Only add new macros for
- * new register offsets, or when the register contents have changed enough to
- * warrant a full redefinition.
- *
- * When a register macro changes for a new platform, prefix the new macro using
- * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
- * prefix signifies the start platform/generation using the register.
- *
- * When a bit (field) macro changes or gets added for a new platform, while
- * retaining the existing register macro, add a platform acronym or generation
- * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
- *
- * Examples
- * ~~~~~~~~
- *
- * (Note that the values in the example are indented using spaces instead of
- * TABs to avoid misalignment in generated documentation. Use TABs in the
- * definitions.)::
- *
- * #define _FOO_A 0xf000
- * #define _FOO_B 0xf001
- * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- * #define FOO_ENABLE REG_BIT(31)
- * #define FOO_MODE_MASK REG_GENMASK(19, 16)
- * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
- * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
- * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
- *
- * #define BAR _MMIO(0xb000)
- * #define GEN8_BAR _MMIO(0xb888)
- */
-
-/**
- * REG_BIT() - Prepare a u32 bit value
- * @__n: 0-based bit number
- *
- * Local wrapper for BIT() to force u32, with compile time checks.
- *
- * @return: Value with bit @__n set.
- */
-#define REG_BIT(__n) \
- ((u32)(BIT(__n) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
- ((__n) < 0 || (__n) > 31))))
-
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
- __is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-
-/*
- * Local integer constant expression version of is_power_of_2().
- */
-#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-
-/**
- * REG_FIELD_PREP() - Prepare a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to put in the field
- *
- * Local copy of FIELD_PREP() to generate an integer constant expression, force
- * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
- *
- * @return: @__val masked and shifted into the field defined by @__mask.
- */
-#define REG_FIELD_PREP(__mask, __val) \
- ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
- BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
- BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
- BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-
-/**
- * REG_FIELD_GET() - Extract a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to extract the bitfield value from
- *
- * Local wrapper for FIELD_GET() to force u32 and for consistency with
- * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
- *
- * @return: Masked and shifted value of the field defined by @__mask in @__val.
- */
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
-
-typedef struct {
- u32 reg;
-} i915_reg_t;
-
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-
-#define INVALID_MMIO_REG _MMIO(0)
-
-static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
-
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
-
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
+#include "i915_reg_types.h"
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
@@ -207,21 +33,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
-/*
- * Given the first two numbers __a and __b of arbitrarily many evenly spaced
- * numbers, pick the 0-based __index'th value.
- *
- * Always prefer this over _PICK() if the numbers are evenly spaced.
- */
-#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
-
-/*
- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
- *
- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
- */
-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
-
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
@@ -259,19 +70,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
-#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
-#define _MASKED_FIELD(mask, value) ({ \
- if (__builtin_constant_p(mask)) \
- BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
- if (__builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
- if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & ~(mask), \
- "Incorrect value for mask"); \
- __MASKED_FIELD(mask, value); })
-#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
-#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-
/* PCI config space */
#define MCHBAR_I915 0x44
new file mode 100644
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2014 Intel Corporation
+ */
+
+#ifndef _I915_REG_TYPES_H_
+#define _I915_REG_TYPES_H_
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+/**
+ * DOC: The i915 register macro definition style guide
+ *
+ * Follow the style described here for new macros, and while changing existing
+ * macros. Do **not** mass change existing definitions just to update the style.
+ *
+ * Layout
+ * ~~~~~~
+ *
+ * Keep helper macros near the top. For example, _PIPE() and friends.
+ *
+ * Prefix macros that generally should not be used outside of this file with
+ * underscore '_'. For example, _PIPE() and friends, single instances of
+ * registers that are defined solely for the use by function-like macros.
+ *
+ * Avoid using the underscore prefixed macros outside of this file. There are
+ * exceptions, but keep them to a minimum.
+ *
+ * There are two basic types of register definitions: Single registers and
+ * register groups. Register groups are registers which have two or more
+ * instances, for example one per pipe, port, transcoder, etc. Register groups
+ * should be defined using function-like macros.
+ *
+ * For single registers, define the register offset first, followed by register
+ * contents.
+ *
+ * For register groups, define the register instance offsets first, prefixed
+ * with underscore, followed by a function-like macro choosing the right
+ * instance based on the parameter, followed by register contents.
+ *
+ * Define the register contents (i.e. bit and bit field macros) from most
+ * significant to least significant bit. Indent the register content macros
+ * using two extra spaces between ``#define`` and the macro name.
+ *
+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
+ * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
+ * shifted in place, so they can be directly OR'd together. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
+ *
+ * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
+ *
+ * Group the register and its contents together without blank lines, separate
+ * from other registers and their contents with one blank line.
+ *
+ * Indent macro values from macro names using TABs. Align values vertically. Use
+ * braces in macro values as needed to avoid unintended precedence after macro
+ * substitution. Use spaces in macro values according to kernel coding
+ * style. Use lower case in hexadecimal values.
+ *
+ * Naming
+ * ~~~~~~
+ *
+ * Try to name registers according to the specs. If the register name changes in
+ * the specs from platform to another, stick to the original name.
+ *
+ * Try to re-use existing register macro definitions. Only add new macros for
+ * new register offsets, or when the register contents have changed enough to
+ * warrant a full redefinition.
+ *
+ * When a register macro changes for a new platform, prefix the new macro using
+ * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
+ * prefix signifies the start platform/generation using the register.
+ *
+ * When a bit (field) macro changes or gets added for a new platform, while
+ * retaining the existing register macro, add a platform acronym or generation
+ * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
+ *
+ * Examples
+ * ~~~~~~~~
+ *
+ * (Note that the values in the example are indented using spaces instead of
+ * TABs to avoid misalignment in generated documentation. Use TABs in the
+ * definitions.)::
+ *
+ * #define _FOO_A 0xf000
+ * #define _FOO_B 0xf001
+ * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
+ * #define FOO_ENABLE REG_BIT(31)
+ * #define FOO_MODE_MASK REG_GENMASK(19, 16)
+ * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
+ * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
+ * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
+ *
+ * #define BAR _MMIO(0xb000)
+ * #define GEN8_BAR _MMIO(0xb888)
+ */
+
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
+/*
+ * Given the first two numbers __a and __b of arbitrarily many evenly spaced
+ * numbers, pick the 0-based __index'th value.
+ *
+ * Always prefer this over _PICK() if the numbers are evenly spaced.
+ */
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
+
+/*
+ * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ *
+ * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ */
+#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+
+#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
+#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
+#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+
+typedef struct {
+ u32 reg;
+} i915_reg_t;
+
+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+
+#define INVALID_MMIO_REG _MMIO(0)
+
+static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
+{
+ return reg.reg;
+}
+
+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
+{
+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
+}
+
+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
+{
+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
+}
+
+#endif
@@ -31,6 +31,7 @@
#include <linux/sysfs.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_sysfs.h"
#include "intel_pm.h"
#include "intel_sideband.h"
@@ -26,6 +26,7 @@
#include "intel_device_info.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
@@ -40,6 +40,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_pm.h"
#include "intel_sideband.h"
@@ -8,7 +8,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_device;
struct drm_i915_private;
@@ -25,6 +25,7 @@
#include <asm/iosf_mbi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_sideband.h"
/*
@@ -25,6 +25,7 @@
#include <asm/iosf_mbi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_pm.h"
@@ -30,7 +30,7 @@
#include <linux/hrtimer.h>
#include <linux/io-64-nonatomic-lo-hi.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
struct intel_runtime_pm;
With the introduction of display uncore, we want to categorize registers between display and non-display. To help us getting it right, it will be useful to move the display registers to a new file that can be used without including i915_reg.h. To allow that, move all the basic register type definitions and helpers to i915_reg_types.h and include that instead of i915_reg.h from header files in the driver. We'll then be able to replace i915_reg.h with the new display-only header in display files and make sure the registers are correctly compartmentalized. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- Documentation/gpu/i915.rst | 4 +- drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_audio.c | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 1 + drivers/gpu/drm/i915/display/intel_cdclk.c | 1 + drivers/gpu/drm/i915/display/intel_color.c | 1 + .../gpu/drm/i915/display/intel_combo_phy.c | 1 + drivers/gpu/drm/i915/display/intel_crt.c | 1 + drivers/gpu/drm/i915/display/intel_crt.h | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_power.c | 1 + .../drm/i915/display/intel_display_power.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_dp.h | 2 +- .../drm/i915/display/intel_dp_link_training.c | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + drivers/gpu/drm/i915/display/intel_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 + drivers/gpu/drm/i915/display/intel_dvo.c | 1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + .../drm/i915/display/intel_fifo_underrun.c | 1 + drivers/gpu/drm/i915/display/intel_gmbus.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.h | 2 +- .../gpu/drm/i915/display/intel_lpe_audio.c | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.h | 2 +- drivers/gpu/drm/i915/display/intel_opregion.c | 1 + drivers/gpu/drm/i915/display/intel_panel.c | 1 + drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 + .../drm/i915/gem/selftests/i915_gem_context.c | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + drivers/gpu/drm/i915/gt/intel_mocs.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 1 + drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + .../gpu/drm/i915/gt/intel_workarounds_types.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +- drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 1 + drivers/gpu/drm/i915/gvt/edid.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/gtt.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.c | 1 + drivers/gpu/drm/i915/gvt/mmio.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gem_fence_reg.c | 1 + drivers/gpu/drm/i915/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_irq.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 204 +---------------- drivers/gpu/drm/i915/i915_reg_types.h | 213 ++++++++++++++++++ drivers/gpu/drm/i915/i915_sysfs.c | 1 + drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + drivers/gpu/drm/i915/intel_pm.h | 2 +- drivers/gpu/drm/i915/intel_sideband.c | 1 + drivers/gpu/drm/i915/intel_uncore.c | 1 + drivers/gpu/drm/i915/intel_uncore.h | 2 +- 101 files changed, 314 insertions(+), 220 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_reg_types.h