| Message ID | 1565703113-31479-3-git-send-email-andrew-sh.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add cpufreq and cci devfreq for mt8183, and SVS support | expand |
On 13-08-19, 21:31, Andrew-sh.Cheng wrote: > From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com> > > Intermediate clock is not always enabled by ccf in different projects, > so cpufreq should always enable it by itself. > > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com> > --- > drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c > index a370577ffc73..acd9539e95de 100644 > --- a/drivers/cpufreq/mediatek-cpufreq.c > +++ b/drivers/cpufreq/mediatek-cpufreq.c > @@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) > goto out_free_resources; > } > > + ret = clk_prepare_enable(inter_clk); > + if (ret) > + goto out_free_opp_table; > + > /* Search a safe voltage for intermediate frequency. */ > rate = clk_get_rate(inter_clk); > opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); > if (IS_ERR(opp)) { > pr_err("failed to get intermediate opp for cpu%d\n", cpu); > ret = PTR_ERR(opp); > - goto out_free_opp_table; > + goto out_disable_clock; > } > info->intermediate_voltage = dev_pm_opp_get_voltage(opp); > dev_pm_opp_put(opp); > @@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) > > return 0; > > +out_disable_clock: > + clk_disable_unprepare(inter_clk); > + > out_free_opp_table: > dev_pm_opp_of_cpumask_remove_table(&info->cpus); > > @@ -419,6 +426,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) > clk_put(info->cpu_clk); > if (!IS_ERR(info->inter_clk)) > clk_put(info->inter_clk); Shouldn't you remove this part now ? > + if (!IS_ERR(info->inter_clk)) { > + clk_disable_unprepare(info->inter_clk); > + clk_put(info->inter_clk); > + } > > dev_pm_opp_of_cpumask_remove_table(&info->cpus); > } > -- > 2.12.5
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index a370577ffc73..acd9539e95de 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -368,13 +368,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_free_opp_table; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -393,6 +397,9 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_clock: + clk_disable_unprepare(inter_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -419,6 +426,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) clk_put(info->cpu_clk); if (!IS_ERR(info->inter_clk)) clk_put(info->inter_clk); + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); + clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); }