| Message ID | 1566109945-11149-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | [RESEND,V2,1/7] arm64: dts: imx8mn-ddr4-evk: Add i2c1 support | expand |
On Sun, Aug 18, 2019 at 02:32:19AM -0400, Anson Huang wrote: > Enable i2c1 on i.MX8MN DDR4 EVK board. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 9b2c172..5fce5b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -50,6 +50,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -182,6 +189,13 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; };
Enable i2c1 on i.MX8MN DDR4 EVK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- No changes. --- arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)