| Message ID | 20190820020147.5667-2-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] drm/i915: Dynamically allocate s0ix struct for VLV | expand |
Quoting Daniele Ceraolo Spurio (2019-08-20 03:01:47) > With the introduction of display uncore, we want to categorize registers > between display and non-display. To help us getting it right, it will > be useful to move the display registers to a new file that can be used > without including i915_reg.h. To allow that, move all the basic register > type definitions and helpers to intel_reg_types.h and include that > instead of i915_reg.h from header files in the driver. We'll then > be able to replace i915_reg.h with the new display-only header in > display files and make sure the registers are correctly > compartmentalized. > > While at it, rename i915_reg.h to intel_reg.h to better indicate that it > contains HW defs. > > v2: use intel_* prefix for register files (Michal) > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> After some mulling, intel_[subsys]_reg.h & intel_reg_types.h workforme, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
Quoting Chris Wilson (2019-08-20 12:16:36) > Quoting Daniele Ceraolo Spurio (2019-08-20 03:01:47) > > With the introduction of display uncore, we want to categorize registers > > between display and non-display. To help us getting it right, it will > > be useful to move the display registers to a new file that can be used > > without including i915_reg.h. To allow that, move all the basic register > > type definitions and helpers to intel_reg_types.h and include that > > instead of i915_reg.h from header files in the driver. We'll then > > be able to replace i915_reg.h with the new display-only header in > > display files and make sure the registers are correctly > > compartmentalized. > > > > While at it, rename i915_reg.h to intel_reg.h to better indicate that it > > contains HW defs. > > > > v2: use intel_* prefix for register files (Michal) > > > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > After some mulling, intel_[subsys]_reg.h & intel_reg_types.h workforme, > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Applied the vlv_s0ix cleanup, but left this as this deserves a few more acks. -Chris
On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: > diff --git a/drivers/gpu/drm/i915/intel_reg_types.h > b/drivers/gpu/drm/i915/intel_reg_types.h > new file mode 100644 > index 000000000000..87bce80dd5ed > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_reg_types.h > + > +typedef struct { > + u32 reg; > +} i915_reg_t; > + > +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) > + > +#define INVALID_MMIO_REG _MMIO(0) > + > +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) > +{ > + return reg.reg; > +} > + > +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) > +{ > + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); > +} > + > +static inline bool i915_mmio_reg_valid(i915_reg_t reg) > +{ > + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); > +} > + hmm, there is now disconnection between prefixes in: 'intel'_reg_types.h and 'i915'_reg_t 'i915'_mmio_reg_xxx() that is why I was suggesting to keep: 'i915'_reg.h (or at your preference 'i915'_reg_types.h) with 'i915'_reg_t 'i915'_mmio_reg_xxx() and use intel_reg* files for actual hw definitions. if we don't plan to rename i915_reg_t into intel_mmio_reg_t then maybe better to stay with i915_reg_types.h ? Michal ps. i915/intel prefix rules are killing me too ;)
On 8/20/19 8:42 AM, Michal Wajdeczko wrote: > On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio > <daniele.ceraolospurio@intel.com> wrote: > > >> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >> b/drivers/gpu/drm/i915/intel_reg_types.h >> new file mode 100644 >> index 000000000000..87bce80dd5ed >> --- /dev/null >> +++ b/drivers/gpu/drm/i915/intel_reg_types.h > > >> + >> +typedef struct { >> + u32 reg; >> +} i915_reg_t; >> + >> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >> + >> +#define INVALID_MMIO_REG _MMIO(0) >> + >> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >> +{ >> + return reg.reg; >> +} >> + >> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >> +{ >> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >> +} >> + >> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> +{ >> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >> +} >> + > > hmm, there is now disconnection between prefixes in: > > 'intel'_reg_types.h > and > 'i915'_reg_t > 'i915'_mmio_reg_xxx() > > that is why I was suggesting to keep: > > 'i915'_reg.h (or at your preference 'i915'_reg_types.h) > with > 'i915'_reg_t > 'i915'_mmio_reg_xxx() > > and use intel_reg* files for actual hw definitions. > > if we don't plan to rename i915_reg_t into intel_mmio_reg_t > then maybe better to stay with i915_reg_types.h ? > I'd personally prefer to keep the intel_* prefix and flip i915_reg_t to intel_reg_t (as a second step to keep things simple). But given the size of the change I'd prefer to hear some more opinions before going through with it, so I'll wait a bit for more comments. Daniele > Michal > > ps. i915/intel prefix rules are killing me too ;)
On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: > > > On 8/20/19 8:42 AM, Michal Wajdeczko wrote: >> On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio >> <daniele.ceraolospurio@intel.com> wrote: >> >> >>> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >>> b/drivers/gpu/drm/i915/intel_reg_types.h >>> new file mode 100644 >>> index 000000000000..87bce80dd5ed >>> --- /dev/null >>> +++ b/drivers/gpu/drm/i915/intel_reg_types.h >> >> >>> + >>> +typedef struct { >>> + u32 reg; >>> +} i915_reg_t; >>> + >>> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >>> + >>> +#define INVALID_MMIO_REG _MMIO(0) >>> + >>> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >>> +{ >>> + return reg.reg; >>> +} >>> + >>> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >>> +{ >>> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >>> +} >>> + >>> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>> +{ >>> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >>> +} >>> + >> >> hmm, there is now disconnection between prefixes in: >> >> 'intel'_reg_types.h >> and >> 'i915'_reg_t >> 'i915'_mmio_reg_xxx() >> >> that is why I was suggesting to keep: >> >> 'i915'_reg.h (or at your preference 'i915'_reg_types.h) >> with >> 'i915'_reg_t >> 'i915'_mmio_reg_xxx() >> >> and use intel_reg* files for actual hw definitions. >> >> if we don't plan to rename i915_reg_t into intel_mmio_reg_t >> then maybe better to stay with i915_reg_types.h ? >> > > I'd personally prefer to keep the intel_* prefix and flip i915_reg_t to > intel_reg_t (as a second step to keep things simple). But given the size > of the change I'd prefer to hear some more opinions before going through > with it, so I'll wait a bit for more comments. > > Daniele > Chris, Jani, are you ok if I got with Michal's suggestion for now, i.e. i915_reg_types.h and intel_reg.h? Daniele >> Michal >> >> ps. i915/intel prefix rules are killing me too ;) > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 22 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: > On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: >> >> >> On 8/20/19 8:42 AM, Michal Wajdeczko wrote: >>> On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio >>> <daniele.ceraolospurio@intel.com> wrote: >>> >>> >>>> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >>>> b/drivers/gpu/drm/i915/intel_reg_types.h >>>> new file mode 100644 >>>> index 000000000000..87bce80dd5ed >>>> --- /dev/null >>>> +++ b/drivers/gpu/drm/i915/intel_reg_types.h >>> >>> >>>> + >>>> +typedef struct { >>>> + u32 reg; >>>> +} i915_reg_t; >>>> + >>>> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >>>> + >>>> +#define INVALID_MMIO_REG _MMIO(0) >>>> + >>>> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >>>> +{ >>>> + return reg.reg; >>>> +} >>>> + >>>> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >>>> +{ >>>> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >>>> +} >>>> + >>>> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>>> +{ >>>> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >>>> +} >>>> + >>> >>> hmm, there is now disconnection between prefixes in: >>> >>> 'intel'_reg_types.h >>> and >>> 'i915'_reg_t >>> 'i915'_mmio_reg_xxx() >>> >>> that is why I was suggesting to keep: >>> >>> 'i915'_reg.h (or at your preference 'i915'_reg_types.h) >>> with >>> 'i915'_reg_t >>> 'i915'_mmio_reg_xxx() >>> >>> and use intel_reg* files for actual hw definitions. >>> >>> if we don't plan to rename i915_reg_t into intel_mmio_reg_t >>> then maybe better to stay with i915_reg_types.h ? >>> >> >> I'd personally prefer to keep the intel_* prefix and flip i915_reg_t to >> intel_reg_t (as a second step to keep things simple). But given the size >> of the change I'd prefer to hear some more opinions before going through >> with it, so I'll wait a bit for more comments. >> >> Daniele >> > > Chris, Jani, are you ok if I got with Michal's suggestion for now, i.e. > i915_reg_types.h and intel_reg.h? There's really nothing in this patch that requires you to rename i915_reg.h at all. The subject of the patch is about adding a new file for the types; the rename seems like an afterthought. I guess we'll add a display/<something>_reg.h later. But that doesn't require this rename either. BR, Jani. > > Daniele > >>> Michal >>> >>> ps. i915/intel prefix rules are killing me too ;) >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 23 Aug 2019, Jani Nikula <jani.nikula@intel.com> wrote: > On Thu, 22 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: >> On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: >>> >>> >>> On 8/20/19 8:42 AM, Michal Wajdeczko wrote: >>>> On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio >>>> <daniele.ceraolospurio@intel.com> wrote: >>>> >>>> >>>>> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >>>>> b/drivers/gpu/drm/i915/intel_reg_types.h >>>>> new file mode 100644 >>>>> index 000000000000..87bce80dd5ed >>>>> --- /dev/null >>>>> +++ b/drivers/gpu/drm/i915/intel_reg_types.h >>>> >>>> >>>>> + >>>>> +typedef struct { >>>>> + u32 reg; >>>>> +} i915_reg_t; >>>>> + >>>>> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >>>>> + >>>>> +#define INVALID_MMIO_REG _MMIO(0) >>>>> + >>>>> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >>>>> +{ >>>>> + return reg.reg; >>>>> +} >>>>> + >>>>> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >>>>> +{ >>>>> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >>>>> +} >>>>> + >>>>> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>>>> +{ >>>>> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >>>>> +} >>>>> + >>>> >>>> hmm, there is now disconnection between prefixes in: >>>> >>>> 'intel'_reg_types.h >>>> and >>>> 'i915'_reg_t >>>> 'i915'_mmio_reg_xxx() >>>> >>>> that is why I was suggesting to keep: >>>> >>>> 'i915'_reg.h (or at your preference 'i915'_reg_types.h) >>>> with >>>> 'i915'_reg_t >>>> 'i915'_mmio_reg_xxx() >>>> >>>> and use intel_reg* files for actual hw definitions. >>>> >>>> if we don't plan to rename i915_reg_t into intel_mmio_reg_t >>>> then maybe better to stay with i915_reg_types.h ? >>>> >>> >>> I'd personally prefer to keep the intel_* prefix and flip i915_reg_t to >>> intel_reg_t (as a second step to keep things simple). But given the size >>> of the change I'd prefer to hear some more opinions before going through >>> with it, so I'll wait a bit for more comments. >>> >>> Daniele >>> >> >> Chris, Jani, are you ok if I got with Michal's suggestion for now, i.e. >> i915_reg_types.h and intel_reg.h? > > There's really nothing in this patch that requires you to rename > i915_reg.h at all. The subject of the patch is about adding a new file > for the types; the rename seems like an afterthought. > > I guess we'll add a display/<something>_reg.h later. But that doesn't > require this rename either. To clarify, I think you can just extract i915_reg_types.h (i915 referring to the *driver* here) from i915_reg.h for starters, and continue with extracting registers to separate files without having to rename i915_reg.h. Make sense? BR, Jani. > > BR, > Jani. > > > >> >> Daniele >> >>>> Michal >>>> >>>> ps. i915/intel prefix rules are killing me too ;) >>> _______________________________________________ >>> Intel-gfx mailing list >>> Intel-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 8/23/19 5:36 AM, Jani Nikula wrote: > On Fri, 23 Aug 2019, Jani Nikula <jani.nikula@intel.com> wrote: >> On Thu, 22 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: >>> On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: >>>> >>>> >>>> On 8/20/19 8:42 AM, Michal Wajdeczko wrote: >>>>> On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio >>>>> <daniele.ceraolospurio@intel.com> wrote: >>>>> >>>>> >>>>>> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >>>>>> b/drivers/gpu/drm/i915/intel_reg_types.h >>>>>> new file mode 100644 >>>>>> index 000000000000..87bce80dd5ed >>>>>> --- /dev/null >>>>>> +++ b/drivers/gpu/drm/i915/intel_reg_types.h >>>>> >>>>> >>>>>> + >>>>>> +typedef struct { >>>>>> + u32 reg; >>>>>> +} i915_reg_t; >>>>>> + >>>>>> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >>>>>> + >>>>>> +#define INVALID_MMIO_REG _MMIO(0) >>>>>> + >>>>>> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >>>>>> +{ >>>>>> + return reg.reg; >>>>>> +} >>>>>> + >>>>>> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >>>>>> +{ >>>>>> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >>>>>> +} >>>>>> + >>>>>> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>>>>> +{ >>>>>> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >>>>>> +} >>>>>> + >>>>> >>>>> hmm, there is now disconnection between prefixes in: >>>>> >>>>> 'intel'_reg_types.h >>>>> and >>>>> 'i915'_reg_t >>>>> 'i915'_mmio_reg_xxx() >>>>> >>>>> that is why I was suggesting to keep: >>>>> >>>>> 'i915'_reg.h (or at your preference 'i915'_reg_types.h) >>>>> with >>>>> 'i915'_reg_t >>>>> 'i915'_mmio_reg_xxx() >>>>> >>>>> and use intel_reg* files for actual hw definitions. >>>>> >>>>> if we don't plan to rename i915_reg_t into intel_mmio_reg_t >>>>> then maybe better to stay with i915_reg_types.h ? >>>>> >>>> >>>> I'd personally prefer to keep the intel_* prefix and flip i915_reg_t to >>>> intel_reg_t (as a second step to keep things simple). But given the size >>>> of the change I'd prefer to hear some more opinions before going through >>>> with it, so I'll wait a bit for more comments. >>>> >>>> Daniele >>>> >>> >>> Chris, Jani, are you ok if I got with Michal's suggestion for now, i.e. >>> i915_reg_types.h and intel_reg.h? >> >> There's really nothing in this patch that requires you to rename >> i915_reg.h at all. The subject of the patch is about adding a new file >> for the types; the rename seems like an afterthought. >> >> I guess we'll add a display/<something>_reg.h later. But that doesn't >> require this rename either. > > To clarify, I think you can just extract i915_reg_types.h (i915 > referring to the *driver* here) from i915_reg.h for starters, and > continue with extracting registers to separate files without having to > rename i915_reg.h. Make sense? > Yes, that's what v1 did, but then I got feedback from Michal to rename i915_reg.h to intel_reg.h. Will flip back to v1 for now and then reconsider the naming once i915_reg.h has been broken up a bit more. Michal, any objection? Daniele > BR, > Jani. > > > > >> >> BR, >> Jani. >> >> >> >>> >>> Daniele >>> >>>>> Michal >>>>> >>>>> ps. i915/intel prefix rules are killing me too ;) >>>> _______________________________________________ >>>> Intel-gfx mailing list >>>> Intel-gfx@lists.freedesktop.org >>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Fri, 23 Aug 2019 16:55:21 +0200, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: > > > On 8/23/19 5:36 AM, Jani Nikula wrote: >> On Fri, 23 Aug 2019, Jani Nikula <jani.nikula@intel.com> wrote: >>> On Thu, 22 Aug 2019, Daniele Ceraolo Spurio >>> <daniele.ceraolospurio@intel.com> wrote: >>>> On 8/20/19 11:00 AM, Daniele Ceraolo Spurio wrote: >>>>> >>>>> >>>>> On 8/20/19 8:42 AM, Michal Wajdeczko wrote: >>>>>> On Tue, 20 Aug 2019 04:01:47 +0200, Daniele Ceraolo Spurio >>>>>> <daniele.ceraolospurio@intel.com> wrote: >>>>>> >>>>>> >>>>>>> diff --git a/drivers/gpu/drm/i915/intel_reg_types.h >>>>>>> b/drivers/gpu/drm/i915/intel_reg_types.h >>>>>>> new file mode 100644 >>>>>>> index 000000000000..87bce80dd5ed >>>>>>> --- /dev/null >>>>>>> +++ b/drivers/gpu/drm/i915/intel_reg_types.h >>>>>> >>>>>> >>>>>>> + >>>>>>> +typedef struct { >>>>>>> + u32 reg; >>>>>>> +} i915_reg_t; >>>>>>> + >>>>>>> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) >>>>>>> + >>>>>>> +#define INVALID_MMIO_REG _MMIO(0) >>>>>>> + >>>>>>> +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) >>>>>>> +{ >>>>>>> + return reg.reg; >>>>>>> +} >>>>>>> + >>>>>>> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) >>>>>>> +{ >>>>>>> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); >>>>>>> +} >>>>>>> + >>>>>>> +static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>>>>>> +{ >>>>>>> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); >>>>>>> +} >>>>>>> + >>>>>> >>>>>> hmm, there is now disconnection between prefixes in: >>>>>> >>>>>> 'intel'_reg_types.h >>>>>> and >>>>>> 'i915'_reg_t >>>>>> 'i915'_mmio_reg_xxx() >>>>>> >>>>>> that is why I was suggesting to keep: >>>>>> >>>>>> 'i915'_reg.h (or at your preference 'i915'_reg_types.h) >>>>>> with >>>>>> 'i915'_reg_t >>>>>> 'i915'_mmio_reg_xxx() >>>>>> >>>>>> and use intel_reg* files for actual hw definitions. >>>>>> >>>>>> if we don't plan to rename i915_reg_t into intel_mmio_reg_t >>>>>> then maybe better to stay with i915_reg_types.h ? >>>>>> >>>>> >>>>> I'd personally prefer to keep the intel_* prefix and flip i915_reg_t >>>>> to >>>>> intel_reg_t (as a second step to keep things simple). But given the >>>>> size >>>>> of the change I'd prefer to hear some more opinions before going >>>>> through >>>>> with it, so I'll wait a bit for more comments. >>>>> >>>>> Daniele >>>>> >>>> >>>> Chris, Jani, are you ok if I got with Michal's suggestion for now, >>>> i.e. >>>> i915_reg_types.h and intel_reg.h? >>> >>> There's really nothing in this patch that requires you to rename >>> i915_reg.h at all. The subject of the patch is about adding a new file >>> for the types; the rename seems like an afterthought. >>> >>> I guess we'll add a display/<something>_reg.h later. But that doesn't >>> require this rename either. >> To clarify, I think you can just extract i915_reg_types.h (i915 >> referring to the *driver* here) from i915_reg.h for starters, and >> continue with extracting registers to separate files without having to >> rename i915_reg.h. Make sense? >> > > Yes, that's what v1 did, but then I got feedback from Michal to rename > i915_reg.h to intel_reg.h. Will flip back to v1 for now and then > reconsider the naming once i915_reg.h has been broken up a bit more. > > Michal, any objection? There was some misunderstanding here. But using i915_reg_types.h for 'i915' types is fine for me. Moving hw register definitions to 'intel' files (to match other files and naming) can be done later (ended by killing empty i915_reg.h) Michal > > Daniele > >> BR, >> Jani. >> >>> >>> BR, >>> Jani. >>> >>> >>> >>>> >>>> Daniele >>>> >>>>>> Michal >>>>>> >>>>>> ps. i915/intel prefix rules are killing me too ;) >>>>> _______________________________________________ >>>>> Intel-gfx mailing list >>>>> Intel-gfx@lists.freedesktop.org >>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 3415255ad3dc..61cace26fcbb 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -576,7 +576,7 @@ cases, deviating from) the kernel coding style. Register macro definition style ------------------------------- -The style guide for ``i915_reg.h``. +The style guide for register definitions in header files. -.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h +.. kernel-doc:: drivers/gpu/drm/i915/intel_reg_types.h :doc: The i915 register macro definition style guide diff --git a/drivers/gpu/drm/i915/display/dvo_ns2501.c b/drivers/gpu/drm/i915/display/dvo_ns2501.c index a724a8755673..8e7ac6035b19 100644 --- a/drivers/gpu/drm/i915/display/dvo_ns2501.c +++ b/drivers/gpu/drm/i915/display/dvo_ns2501.c @@ -27,9 +27,9 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_display_types.h" #include "intel_dvo_dev.h" +#include "intel_reg.h" #define NS2501_VID 0x1305 #define NS2501_DID 0x6726 diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 6e398c33a524..377f7a699c6c 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -34,6 +34,7 @@ #include "intel_ddi.h" #include "intel_dsi.h" #include "intel_panel.h" +#include "intel_reg.h" static inline int header_credits_available(struct drm_i915_private *dev_priv, enum transcoder dsi_trans) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index d3fb75bb9eb1..5c7c040bd397 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -37,6 +37,7 @@ #include "intel_atomic.h" #include "intel_display_types.h" #include "intel_hdcp.h" +#include "intel_reg.h" #include "intel_sprite.h" /** diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index ddcccf4408c3..f91750b8c3a0 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -31,6 +31,7 @@ #include "intel_audio.h" #include "intel_display_types.h" #include "intel_lpe_audio.h" +#include "intel_reg.h" /** * DOC: High Definition Audio over HDMI and Display Port diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 688858ebe4d0..2b3529e3115f 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -7,6 +7,7 @@ #include "intel_bw.h" #include "intel_display_types.h" +#include "intel_reg.h" #include "intel_sideband.h" /* Parameters for Qclk Geyserville (QGV) */ diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index d0bc42e5039c..cd5fc8234376 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -23,6 +23,7 @@ #include "intel_cdclk.h" #include "intel_display_types.h" +#include "intel_reg.h" #include "intel_sideband.h" /** diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 71a0201437a9..b8bb7439001e 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -24,6 +24,7 @@ #include "intel_color.h" #include "intel_display_types.h" +#include "intel_reg.h" #define CTM_COEFF_SIGN (1ULL << 63) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 44bbc7e74fc3..421ccaad513a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -5,6 +5,7 @@ #include "intel_combo_phy.h" #include "intel_display_types.h" +#include "intel_reg.h" #define for_each_combo_phy(__dev_priv, __phy) \ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index e6e8d4a82044..26f56c3b9175 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -42,6 +42,7 @@ #include "intel_fifo_underrun.h" #include "intel_gmbus.h" #include "intel_hotplug.h" +#include "intel_reg.h" /* Here's the desired hotplug mode */ #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index 1b3fba359efc..fa1c45cb781c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -6,7 +6,7 @@ #ifndef __INTEL_CRT_H__ #define __INTEL_CRT_H__ -#include "i915_reg.h" +#include "intel_reg_types.h" enum pipe; struct drm_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1f591e69b742..298cd35ee4d7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -45,6 +45,7 @@ #include "intel_lspcon.h" #include "intel_panel.h" #include "intel_psr.h" +#include "intel_reg.h" #include "intel_tc.h" #include "intel_vdsc.h" diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee54d9659c99..280d36dee3bd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -76,6 +76,7 @@ #include "intel_pm.h" #include "intel_psr.h" #include "intel_quirks.h" +#include "intel_reg.h" #include "intel_sideband.h" #include "intel_sprite.h" #include "intel_tc.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 02f8c3911c59..df0d2922d861 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -17,6 +17,7 @@ #include "intel_display_types.h" #include "intel_dpio_phy.h" #include "intel_hotplug.h" +#include "intel_reg.h" #include "intel_sideband.h" #include "intel_tc.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index a50605b8b1ad..1181e2d8c128 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -7,8 +7,8 @@ #define __INTEL_DISPLAY_POWER_H__ #include "intel_display.h" +#include "intel_reg_types.h" #include "intel_runtime_pm.h" -#include "i915_reg.h" struct drm_i915_private; struct intel_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5c45a3bb102d..cfb325a8589e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -62,6 +62,7 @@ #include "intel_lvds.h" #include "intel_panel.h" #include "intel_psr.h" +#include "intel_reg.h" #include "intel_sideband.h" #include "intel_tc.h" #include "intel_vdsc.h" diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 657bbb1f5ed0..477142d77267 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -10,7 +10,7 @@ #include <drm/i915_drm.h> -#include "i915_reg.h" +#include "intel_reg_types.h" enum pipe; struct drm_connector_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 2a1130dd1ad0..799b66f7bee0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -24,6 +24,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_reg.h" static void intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 83faa246e361..c5a8a118e4e7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -36,6 +36,7 @@ #include "intel_dp.h" #include "intel_dp_mst.h" #include "intel_dpio_phy.h" +#include "intel_reg.h" static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 556d1b30f06a..5db15c91bf2c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dpio_phy.h" +#include "intel_reg.h" #include "intel_sideband.h" /** diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b8148f838354..ce7a0cedaa0b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -24,6 +24,7 @@ #include "intel_display_types.h" #include "intel_dpio_phy.h" #include "intel_dpll_mgr.h" +#include "intel_reg.h" /** * DOC: Display PLLs diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c index 5fec02aceaed..6998dd8eb1c2 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.c +++ b/drivers/gpu/drm/i915/display/intel_dsi.c @@ -5,6 +5,7 @@ #include <drm/drm_mipi_dsi.h> #include "intel_dsi.h" +#include "intel_reg.h" int intel_dsi_bitrate(const struct intel_dsi *intel_dsi) { diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index f90946c912ee..da0ca6d61ba9 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -40,6 +40,7 @@ #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dsi.h" +#include "intel_reg.h" #include "intel_sideband.h" #define MIPI_TRANSFER_MODE_SHIFT 0 diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 93baf366692e..9bc3b4b632b9 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -39,6 +39,7 @@ #include "intel_dvo_dev.h" #include "intel_gmbus.h" #include "intel_panel.h" +#include "intel_reg.h" #define INTEL_DVO_CHIP_NONE 0 #define INTEL_DVO_CHIP_LVDS 1 diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h index 94a6ae1e0292..78b264daf5f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h +++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h @@ -27,7 +27,7 @@ #include <drm/drm_crtc.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct intel_dvo_device { const char *name; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 16ed44bfd734..554199aa37fa 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -44,6 +44,7 @@ #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_frontbuffer.h" +#include "intel_reg.h" static inline bool fbc_supported(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index ab61f88d1d33..a9dbad6f5567 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -30,6 +30,7 @@ #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_fifo_underrun.h" +#include "intel_reg.h" /** * DOC: fifo underrun handling diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index d6775a005726..0bf4c5b37544 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -37,6 +37,7 @@ #include "i915_drv.h" #include "intel_display_types.h" #include "intel_gmbus.h" +#include "intel_reg.h" struct gmbus_pin { const char *name; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 6ec5ceeab601..cc648c3293b3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -13,10 +13,10 @@ #include <drm/drm_hdcp.h> #include <drm/i915_component.h> -#include "i915_reg.h" #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_hdcp.h" +#include "intel_reg.h" #include "intel_sideband.h" #define KEY_LOAD_TRIES 5 diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index b1ca8e5bdb56..8a6398c283fa 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -55,6 +55,7 @@ #include "intel_hotplug.h" #include "intel_lspcon.h" #include "intel_panel.h" +#include "intel_reg.h" #include "intel_sdvo.h" #include "intel_sideband.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 106c2e0bc3c9..4cf0c3226e33 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -11,7 +11,7 @@ #include <drm/i915_drm.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct drm_connector; struct drm_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index b19800b58442..7c19d5aa12ad 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -72,6 +72,7 @@ #include "i915_drv.h" #include "intel_lpe_audio.h" +#include "intel_reg.h" #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index f8f1308643a9..7d1a2a3c621e 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -30,6 +30,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_lspcon.h" +#include "intel_reg.h" /* LSPCON OUI Vendor ID(signatures) */ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index b7c459a8931c..51b9a188faef 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -46,6 +46,7 @@ #include "intel_gmbus.h" #include "intel_lvds.h" #include "intel_panel.h" +#include "intel_reg.h" /* Private structure for the integrated LVDS support */ struct intel_lvds_pps { diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h index bc9c8b84ba2f..fb22578179e7 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.h +++ b/drivers/gpu/drm/i915/display/intel_lvds.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg.h" +#include "intel_reg_types.h" enum pipe; struct drm_i915_private; diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 969ade623691..4fa7cb0eef84 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -37,6 +37,7 @@ #include "i915_drv.h" #include "intel_display_types.h" #include "intel_opregion.h" +#include "intel_reg.h" #define OPREGION_HEADER_OFFSET 0 #define OPREGION_ACPI_OFFSET 0x100 diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index eca41c4a5aa6..61b7c0f27bb3 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -32,10 +32,10 @@ #include "gem/i915_gem_pm.h" #include "i915_drv.h" -#include "i915_reg.h" #include "intel_display_types.h" #include "intel_frontbuffer.h" #include "intel_overlay.h" +#include "intel_reg.h" /* Limits for overlay size. According to intel doc, the real limits are: * Y width: 4095, UV width (planar): 2047, Y height: 2047, diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index bc14e9c0285a..fd4b0433df94 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -39,6 +39,7 @@ #include "intel_dp_aux_backlight.h" #include "intel_dsi_dcs_backlight.h" #include "intel_panel.h" +#include "intel_reg.h" #define CRC_PMIC_PWM_PERIOD_NS 21333 diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 6260a2082719..15a38587c2a5 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -32,6 +32,7 @@ #include "intel_atomic.h" #include "intel_display_types.h" #include "intel_pipe_crc.h" +#include "intel_reg.h" static const char * const pipe_crc_sources[] = { [INTEL_PIPE_CRC_SOURCE_NONE] = "none", diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3bfb720560c2..6ef056c20f70 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -28,6 +28,7 @@ #include "i915_drv.h" #include "intel_display_types.h" #include "intel_psr.h" +#include "intel_reg.h" #include "intel_sprite.h" /** diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index adeb1c840976..8ca19d551a5a 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -45,6 +45,7 @@ #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_panel.h" +#include "intel_reg.h" #include "intel_sdvo.h" #include "intel_sdvo_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index c9e05bcdd141..821c0d963a36 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -10,7 +10,7 @@ #include <drm/i915_drm.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct drm_i915_private; enum pipe; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index dea63be1964f..efcf162ad3c5 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -46,6 +46,7 @@ #include "intel_frontbuffer.h" #include "intel_pm.h" #include "intel_psr.h" +#include "intel_reg.h" #include "intel_sprite.h" bool is_planar_yuv_format(u32 pixelformat) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 85743a43bee2..ad113023d012 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -7,6 +7,7 @@ #include "intel_display.h" #include "intel_display_types.h" #include "intel_dp_mst.h" +#include "intel_reg.h" #include "intel_tc.h" static const char *tc_port_mode_name(enum tc_port_mode mode) diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index b70221f5112a..c4e6b3820de1 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -39,6 +39,7 @@ #include "intel_connector.h" #include "intel_display_types.h" #include "intel_hotplug.h" +#include "intel_reg.h" #include "intel_tv.h" enum tv_margin { diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 598ddb60f9fb..c6dc6549efb8 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,6 +10,7 @@ #include "i915_drv.h" #include "intel_display_types.h" +#include "intel_reg.h" #include "intel_vdsc.h" enum ROW_INDEX_BPP { diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index a71b22bdd95b..be305b89e444 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -38,6 +38,7 @@ #include "intel_dsi.h" #include "intel_fifo_underrun.h" #include "intel_panel.h" +#include "intel_reg.h" #include "intel_sideband.h" /* return pixels in terms of txbyteclkhs */ diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index 95f39cd0ce02..4cdffd75bce1 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -30,6 +30,7 @@ #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dsi.h" +#include "intel_reg.h" #include "intel_sideband.h" static const u16 lfsr_converts[] = { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index cd1fd2e5423a..a611bdb1a1ac 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -76,6 +76,7 @@ #include "i915_globals.h" #include "i915_trace.h" #include "i915_user_extensions.h" +#include "intel_reg.h" #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 53752006d307..65147ca87526 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -25,6 +25,7 @@ #include "i915_gem_context.h" #include "i915_gem_ioctls.h" #include "i915_trace.h" +#include "intel_reg.h" enum { FORCE_CPU_RELOC = 1, diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 48c2cbe9b278..f4fc1e41f0fd 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -15,6 +15,7 @@ #include "i915_gem_object.h" #include "i915_trace.h" #include "i915_vma.h" +#include "intel_reg.h" static inline bool __vma_matches(struct vm_area_struct *vma, struct file *filp, diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index aa533b4ab5f5..149e6d647795 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -12,6 +12,7 @@ #include "i915_drv.h" #include "i915_gem_stolen.h" +#include "intel_reg.h" /* * The BIOS typically reserves some of the system's memory for the exclusive diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index ca0c2f451742..d889d5bbe223 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -12,6 +12,7 @@ #include "i915_gem.h" #include "i915_gem_ioctls.h" #include "i915_gem_object.h" +#include "intel_reg.h" /** * DOC: buffer object tiling diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 3e6f4a65d356..a1c51014012e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -10,6 +10,7 @@ #include "gt/intel_gt.h" #include "gt/intel_reset.h" #include "i915_selftest.h" +#include "intel_reg.h" #include "gem/selftests/igt_gem_utils.h" #include "selftests/i915_random.h" diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index d3c6993f4f46..4986708e98d0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -10,12 +10,12 @@ #include <linux/seqlock.h> #include "i915_pmu.h" -#include "i915_reg.h" #include "i915_request.h" #include "i915_selftest.h" #include "gt/intel_timeline.h" #include "intel_engine_types.h" #include "intel_gpu_commands.h" +#include "intel_reg_types.h" #include "intel_workarounds.h" struct drm_printer; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index ba457c1c7dc0..b84aa336deca 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -27,6 +27,7 @@ #include "gem/i915_gem_context.h" #include "i915_drv.h" +#include "intel_reg.h" #include "gt/intel_gt.h" diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d48ec9a76ed1..4a9fb5eea03b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "intel_gt.h" #include "intel_gt_pm.h" +#include "intel_reg.h" #include "intel_uncore.h" void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 34a4fb624bf7..37c559f1e148 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -10,6 +10,7 @@ #include "i915_irq.h" #include "intel_gt.h" #include "intel_gt_irq.h" +#include "intel_reg.h" #include "intel_uncore.h" static void guc_irq_handler(struct intel_guc *guc, u16 iir) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c index babe866126d7..159a6581bdb1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c @@ -5,10 +5,10 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_gt.h" #include "intel_gt_irq.h" #include "intel_gt_pm_irq.h" +#include "intel_reg.h" static void write_pm_imr(struct intel_gt *gt) { diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c index 05d042cdefe2..c4d5b89eeae2 100644 --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c @@ -25,6 +25,7 @@ #include "i915_drv.h" #include "intel_engine.h" #include "intel_gt.h" +#include "intel_reg.h" #include "intel_reset.h" struct hangcheck { diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d2800dc7fa4f..a20b6ed9a884 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -144,6 +144,7 @@ #include "intel_gt_pm.h" #include "intel_lrc_reg.h" #include "intel_mocs.h" +#include "intel_reg.h" #include "intel_reset.h" #include "intel_workarounds.h" diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 728704bbbe18..9d989a876e55 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -21,6 +21,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "intel_engine.h" #include "intel_gt.h" diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 077716442c90..44e5917b9f7e 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -18,6 +18,7 @@ #include "intel_engine_pm.h" #include "intel_gt.h" #include "intel_gt_pm.h" +#include "intel_reg.h" #include "intel_reset.h" #include "uc/intel_guc.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c index 601c16239fdf..c28dcb329fec 100644 --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c @@ -39,6 +39,7 @@ #include "intel_gt.h" #include "intel_gt_irq.h" #include "intel_gt_pm_irq.h" +#include "intel_reg.h" #include "intel_reset.h" #include "intel_workarounds.h" diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 6bf2d87da109..734bae4821cf 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "intel_lrc_reg.h" +#include "intel_reg.h" #include "intel_sseu.h" unsigned int diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 704ace01e7f5..397f926524b8 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -7,6 +7,7 @@ #include "i915_drv.h" #include "intel_context.h" #include "intel_gt.h" +#include "intel_reg.h" #include "intel_workarounds.h" /** diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h index e27ab1b710b3..a3ec2eccaf76 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h @@ -9,7 +9,7 @@ #include <linux/types.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct i915_wa { i915_reg_t reg; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c index 5528224448f6..fa4fe1db6084 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c @@ -11,7 +11,9 @@ #include "gt/intel_gt.h" #include "intel_guc_fw.h" + #include "i915_drv.h" +#include "intel_reg.h" /** * intel_guc_fw_init_early() - initializes GuC firmware struct diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index edf194d23c6b..1865e2aca31e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -9,7 +9,7 @@ #include <linux/compiler.h> #include <linux/types.h> -#include "i915_reg.h" +#include "intel_reg_types.h" /* Definitions of GuC H/W registers, bits, etc */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index f325d3dd564f..c173f32a662e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -16,6 +16,7 @@ #include "i915_drv.h" #include "i915_trace.h" +#include "intel_reg.h" enum { GUC_PREEMPT_NONE = 0, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h index 644c059fe01d..faf01e55a85b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h @@ -6,9 +6,9 @@ #ifndef _INTEL_HUC_H_ #define _INTEL_HUC_H_ -#include "i915_reg.h" #include "intel_uc_fw.h" #include "intel_huc_fw.h" +#include "intel_reg_types.h" struct intel_huc { /* Generic uC firmware management */ diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index c3d19d88da40..28e5b35de5bc 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -36,6 +36,7 @@ #include "i915_drv.h" #include "i915_gem_fence_reg.h" +#include "intel_reg.h" #include "gvt.h" static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index e753b1e706e2..a3f5dde84d71 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -38,6 +38,7 @@ #include "i915_drv.h" #include "gvt.h" #include "i915_pvinfo.h" +#include "intel_reg.h" #include "trace.h" #define INVALID_OP (~0U) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index e1c313da6c00..c1d8aa6e8403 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -33,6 +33,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" static int get_edp_pipe(struct intel_vgpu *vgpu) diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 13044c027f27..6d3d4e5f1a38 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -32,6 +32,7 @@ #include <linux/vfio.h> #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12)) diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 1fe6124918f1..ba61103bdcdc 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -33,6 +33,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" #define GMBUS1_TOTAL_BYTES_SHIFT 16 diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 8bb292b01271..aa726dbec8ed 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -37,6 +37,7 @@ #include "i915_drv.h" #include "gvt.h" #include "i915_pvinfo.h" +#include "intel_reg.h" #define PRIMARY_FORMAT_NUM 16 struct pixel_format { diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 4b04af569c05..e3f46d00eb90 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -36,6 +36,7 @@ #include "i915_drv.h" #include "gvt.h" #include "i915_pvinfo.h" +#include "intel_reg.h" #include "trace.h" #if defined(VERBOSE_DEBUG) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 25f78196b964..e814e125256b 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -39,6 +39,7 @@ #include "i915_drv.h" #include "gvt.h" #include "i915_pvinfo.h" +#include "intel_reg.h" /* XXX FIXME i915 has changed PP_XXX definition */ #define PCH_PP_STATUS _MMIO(0xc7200) diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c index 11accd3e1023..488935a40cfe 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.c +++ b/drivers/gpu/drm/i915/gvt/interrupt.c @@ -30,6 +30,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" #include "trace.h" diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c index a55178884d67..efa07e9b36c3 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.c +++ b/drivers/gpu/drm/i915/gvt/mmio.c @@ -34,6 +34,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" /** diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 4208e40445b1..6f7fe56efa04 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -34,6 +34,7 @@ */ #include "i915_drv.h" +#include "intel_reg.h" #include "gt/intel_context.h" #include "gvt.h" #include "trace.h" diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 8940fa8d391a..547fe04723cf 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -40,6 +40,7 @@ #include "gt/intel_context.h" #include "i915_drv.h" +#include "intel_reg.h" #include "gvt.h" #define RING_CTX_OFF(x) \ diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 24555102e198..8f70bc16f913 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -29,6 +29,7 @@ #include "i915_drv.h" #include "i915_memcpy.h" +#include "intel_reg.h" /** * DOC: batch buffer command parser diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b39226d7f8d2..50f948b9ed04 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -49,6 +49,7 @@ #include "i915_trace.h" #include "intel_csr.h" #include "intel_pm.h" +#include "intel_reg.h" #include "intel_sideband.h" static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b5b2a64753e6..4d4b2815fd13 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -77,6 +77,7 @@ #include "i915_vgpu.h" #include "intel_csr.h" #include "intel_pm.h" +#include "intel_reg.h" static struct drm_driver driver; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ba6d9bb127d7..9f156e22a1c7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -60,7 +60,6 @@ #include "i915_fixed.h" #include "i915_params.h" -#include "i915_reg.h" #include "i915_utils.h" #include "display/intel_bios.h" @@ -83,6 +82,7 @@ #include "intel_device_info.h" #include "intel_pch.h" +#include "intel_reg_types.h" #include "intel_runtime_pm.h" #include "intel_uncore.h" #include "intel_wakeref.h" diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 22021da28239..96478decb1db 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -60,6 +60,7 @@ #include "i915_vgpu.h" #include "intel_pm.h" +#include "intel_reg.h" static int insert_mappable_node(struct i915_ggtt *ggtt, diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index c9654f1a468f..697ebe80d13c 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -26,6 +26,7 @@ #include "i915_drv.h" #include "i915_scatterlist.h" #include "i915_vgpu.h" +#include "intel_reg.h" /** * DOC: fence register handling diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 5413c2ff51a2..d6edeba496f4 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -42,6 +42,7 @@ #include "i915_scatterlist.h" #include "i915_trace.h" #include "i915_vgpu.h" +#include "intel_reg.h" #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index e284bd76fa86..ffe72a798b64 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -46,6 +46,7 @@ #include "i915_memcpy.h" #include "i915_scatterlist.h" #include "intel_csr.h" +#include "intel_reg.h" #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 37e3dd3c1a9d..00259e4cc554 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -51,6 +51,7 @@ #include "i915_irq.h" #include "i915_trace.h" #include "intel_pm.h" +#include "intel_reg.h" /** * DOC: interrupt handling diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 8e7e6071777e..2be53d603efe 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -10,7 +10,7 @@ #include <linux/types.h> #include "display/intel_display.h" -#include "i915_reg.h" +#include "intel_reg_types.h" struct drm_crtc; struct drm_device; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 1974e4c78a43..22bf11131840 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -33,6 +33,7 @@ #include "i915_drv.h" #include "i915_globals.h" #include "i915_selftest.h" +#include "intel_reg.h" #define PLATFORM(x) .platform = (x) #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index e42b86827d6b..30cfe84d05c4 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -201,6 +201,7 @@ #include "i915_drv.h" #include "i915_perf.h" +#include "intel_reg.h" #include "oa/i915_oa_hsw.h" #include "oa/i915_oa_bdw.h" #include "oa/i915_oa_chv.h" diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 8e251e719390..84f473e97e35 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -15,6 +15,7 @@ #include "i915_drv.h" #include "i915_pmu.h" #include "intel_pm.h" +#include "intel_reg.h" /* Frequency for the sampling timer for events which need it. */ #define FREQUENCY 200 diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 8508a01ad8b9..a080d1de660e 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -30,8 +30,8 @@ #include "display/intel_gmbus.h" #include "i915_drv.h" -#include "i915_reg.h" #include "i915_suspend.h" +#include "intel_reg.h" static void i915_save_display(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index d8a3b180c084..56cc75178ca4 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -33,6 +33,7 @@ #include "i915_drv.h" #include "i915_sysfs.h" #include "intel_pm.h" +#include "intel_reg.h" #include "intel_sideband.h" static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 8279e72edf4c..8c87561fa750 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -25,8 +25,8 @@ #include <linux/firmware.h> #include "i915_drv.h" -#include "i915_reg.h" #include "intel_csr.h" +#include "intel_reg.h" /** * DOC: csr support for dmc diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index f99c9fd497b2..291b9a99bfdc 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -25,6 +25,7 @@ #include <drm/drm_print.h> #include "intel_device_info.h" +#include "intel_reg.h" #include "i915_drv.h" #define PLATFORM_NAME(x) [INTEL_##x] = #x diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aca676e79948..ee78968b2c9f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -42,6 +42,7 @@ #include "i915_irq.h" #include "i915_trace.h" #include "intel_pm.h" +#include "intel_reg.h" #include "intel_sideband.h" #include "../../../platform/x86/intel_ips.h" diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index e3573e1e16e3..b6a392c52e8a 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct drm_device; struct drm_i915_private; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/intel_reg.h similarity index 98% rename from drivers/gpu/drm/i915/i915_reg.h rename to drivers/gpu/drm/i915/intel_reg.h index ea2f0fa2402d..59e6466aa385 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/intel_reg.h @@ -22,184 +22,10 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef _I915_REG_H_ -#define _I915_REG_H_ +#ifndef _INTEL_REG_H_ +#define _INTEL_REG_H_ -#include <linux/bitfield.h> -#include <linux/bits.h> - -/** - * DOC: The i915 register macro definition style guide - * - * Follow the style described here for new macros, and while changing existing - * macros. Do **not** mass change existing definitions just to update the style. - * - * Layout - * ~~~~~~ - * - * Keep helper macros near the top. For example, _PIPE() and friends. - * - * Prefix macros that generally should not be used outside of this file with - * underscore '_'. For example, _PIPE() and friends, single instances of - * registers that are defined solely for the use by function-like macros. - * - * Avoid using the underscore prefixed macros outside of this file. There are - * exceptions, but keep them to a minimum. - * - * There are two basic types of register definitions: Single registers and - * register groups. Register groups are registers which have two or more - * instances, for example one per pipe, port, transcoder, etc. Register groups - * should be defined using function-like macros. - * - * For single registers, define the register offset first, followed by register - * contents. - * - * For register groups, define the register instance offsets first, prefixed - * with underscore, followed by a function-like macro choosing the right - * instance based on the parameter, followed by register contents. - * - * Define the register contents (i.e. bit and bit field macros) from most - * significant to least significant bit. Indent the register content macros - * using two extra spaces between ``#define`` and the macro name. - * - * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents - * using ``REG_FIELD_PREP(mask, value)``. This will define the values already - * shifted in place, so they can be directly OR'd together. For convenience, - * function-like macros may be used to define bit fields, but do note that the - * macros may be needed to read as well as write the register contents. - * - * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. - * - * Group the register and its contents together without blank lines, separate - * from other registers and their contents with one blank line. - * - * Indent macro values from macro names using TABs. Align values vertically. Use - * braces in macro values as needed to avoid unintended precedence after macro - * substitution. Use spaces in macro values according to kernel coding - * style. Use lower case in hexadecimal values. - * - * Naming - * ~~~~~~ - * - * Try to name registers according to the specs. If the register name changes in - * the specs from platform to another, stick to the original name. - * - * Try to re-use existing register macro definitions. Only add new macros for - * new register offsets, or when the register contents have changed enough to - * warrant a full redefinition. - * - * When a register macro changes for a new platform, prefix the new macro using - * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The - * prefix signifies the start platform/generation using the register. - * - * When a bit (field) macro changes or gets added for a new platform, while - * retaining the existing register macro, add a platform acronym or generation - * suffix to the name. For example, ``_SKL`` or ``_GEN8``. - * - * Examples - * ~~~~~~~~ - * - * (Note that the values in the example are indented using spaces instead of - * TABs to avoid misalignment in generated documentation. Use TABs in the - * definitions.):: - * - * #define _FOO_A 0xf000 - * #define _FOO_B 0xf001 - * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) - * #define FOO_ENABLE REG_BIT(31) - * #define FOO_MODE_MASK REG_GENMASK(19, 16) - * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) - * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) - * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) - * - * #define BAR _MMIO(0xb000) - * #define GEN8_BAR _MMIO(0xb888) - */ - -/** - * REG_BIT() - Prepare a u32 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u32, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT(__n) \ - ((u32)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 31)))) - -/** - * REG_GENMASK() - Prepare a continuous u32 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u32, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK(__high, __low) \ - ((u32)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) - -/* - * Local integer constant expression version of is_power_of_2(). - */ -#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) - -/** - * REG_FIELD_PREP() - Prepare a u32 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to put in the field - * - * Local copy of FIELD_PREP() to generate an integer constant expression, force - * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). - * - * @return: @__val masked and shifted into the field defined by @__mask. - */ -#define REG_FIELD_PREP(__mask, __val) \ - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) - -/** - * REG_FIELD_GET() - Extract a u32 bitfield value - * @__mask: shifted mask defining the field's length and position - * @__val: value to extract the bitfield value from - * - * Local wrapper for FIELD_GET() to force u32 and for consistency with - * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). - * - * @return: Masked and shifted value of the field defined by @__mask in @__val. - */ -#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) - -typedef struct { - u32 reg; -} i915_reg_t; - -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) - -#define INVALID_MMIO_REG _MMIO(0) - -static inline u32 i915_mmio_reg_offset(i915_reg_t reg) -{ - return reg.reg; -} - -static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) -{ - return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); -} - -static inline bool i915_mmio_reg_valid(i915_reg_t reg) -{ - return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); -} +#include "intel_reg_types.h" #define VLV_DISPLAY_BASE 0x180000 #define VLV_MIPI_BASE VLV_DISPLAY_BASE @@ -207,21 +33,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) -/* - * Given the first two numbers __a and __b of arbitrarily many evenly spaced - * numbers, pick the 0-based __index'th value. - * - * Always prefer this over _PICK() if the numbers are evenly spaced. - */ -#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) - -/* - * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. - * - * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. - */ -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) - /* * Named helper wrappers around _PICK_EVEN() and _PICK(). */ @@ -259,19 +70,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv)) -#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) -#define _MASKED_FIELD(mask, value) ({ \ - if (__builtin_constant_p(mask)) \ - BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ - if (__builtin_constant_p(value)) \ - BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ - if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ - BUILD_BUG_ON_MSG((value) & ~(mask), \ - "Incorrect value for mask"); \ - __MASKED_FIELD(mask, value); }) -#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) -#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) - /* PCI config space */ #define MCHBAR_I915 0x44 @@ -11538,4 +11336,4 @@ enum skl_power_gate { #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port)) -#endif /* _I915_REG_H_ */ +#endif /* _INTEL_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_reg_types.h b/drivers/gpu/drm/i915/intel_reg_types.h new file mode 100644 index 000000000000..87bce80dd5ed --- /dev/null +++ b/drivers/gpu/drm/i915/intel_reg_types.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef _INTEL_REG_TYPES_H_ +#define _INTEL_REG_TYPES_H_ + +#include <linux/bitfield.h> +#include <linux/bits.h> + +/** + * DOC: The i915 register macro definition style guide + * + * Follow the style described here for new macros, and while changing existing + * macros. Do **not** mass change existing definitions just to update the style. + * + * Layout + * ~~~~~~ + * + * Keep helper macros near the top. For example, _PIPE() and friends. + * + * Prefix macros that generally should not be used outside of this file with + * underscore '_'. For example, _PIPE() and friends, single instances of + * registers that are defined solely for the use by function-like macros. + * + * Avoid using the underscore prefixed macros outside of this file. There are + * exceptions, but keep them to a minimum. + * + * There are two basic types of register definitions: Single registers and + * register groups. Register groups are registers which have two or more + * instances, for example one per pipe, port, transcoder, etc. Register groups + * should be defined using function-like macros. + * + * For single registers, define the register offset first, followed by register + * contents. + * + * For register groups, define the register instance offsets first, prefixed + * with underscore, followed by a function-like macro choosing the right + * instance based on the parameter, followed by register contents. + * + * Define the register contents (i.e. bit and bit field macros) from most + * significant to least significant bit. Indent the register content macros + * using two extra spaces between ``#define`` and the macro name. + * + * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents + * using ``REG_FIELD_PREP(mask, value)``. This will define the values already + * shifted in place, so they can be directly OR'd together. For convenience, + * function-like macros may be used to define bit fields, but do note that the + * macros may be needed to read as well as write the register contents. + * + * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. + * + * Group the register and its contents together without blank lines, separate + * from other registers and their contents with one blank line. + * + * Indent macro values from macro names using TABs. Align values vertically. Use + * braces in macro values as needed to avoid unintended precedence after macro + * substitution. Use spaces in macro values according to kernel coding + * style. Use lower case in hexadecimal values. + * + * Naming + * ~~~~~~ + * + * Try to name registers according to the specs. If the register name changes in + * the specs from platform to another, stick to the original name. + * + * Try to re-use existing register macro definitions. Only add new macros for + * new register offsets, or when the register contents have changed enough to + * warrant a full redefinition. + * + * When a register macro changes for a new platform, prefix the new macro using + * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The + * prefix signifies the start platform/generation using the register. + * + * When a bit (field) macro changes or gets added for a new platform, while + * retaining the existing register macro, add a platform acronym or generation + * suffix to the name. For example, ``_SKL`` or ``_GEN8``. + * + * Examples + * ~~~~~~~~ + * + * (Note that the values in the example are indented using spaces instead of + * TABs to avoid misalignment in generated documentation. Use TABs in the + * definitions.):: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf001 + * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) + * #define FOO_ENABLE REG_BIT(31) + * #define FOO_MODE_MASK REG_GENMASK(19, 16) + * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) + * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) + * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) + * + * #define BAR _MMIO(0xb000) + * #define GEN8_BAR _MMIO(0xb888) + */ + +/** + * REG_BIT() - Prepare a u32 bit value + * @__n: 0-based bit number + * + * Local wrapper for BIT() to force u32, with compile time checks. + * + * @return: Value with bit @__n set. + */ +#define REG_BIT(__n) \ + ((u32)(BIT(__n) + \ + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ + ((__n) < 0 || (__n) > 31)))) + +/** + * REG_GENMASK() - Prepare a continuous u32 bitmask + * @__high: 0-based high bit + * @__low: 0-based low bit + * + * Local wrapper for GENMASK() to force u32, with compile time checks. + * + * @return: Continuous bitmask from @__high to @__low, inclusive. + */ +#define REG_GENMASK(__high, __low) \ + ((u32)(GENMASK(__high, __low) + \ + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ + __is_constexpr(__low) && \ + ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) + +/* + * Local integer constant expression version of is_power_of_2(). + */ +#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) + +/** + * REG_FIELD_PREP() - Prepare a u32 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP() to generate an integer constant expression, force + * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP(__mask, __val) \ + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) + +/** + * REG_FIELD_GET() - Extract a u32 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to extract the bitfield value from + * + * Local wrapper for FIELD_GET() to force u32 and for consistency with + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). + * + * @return: Masked and shifted value of the field defined by @__mask in @__val. + */ +#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) + +/* + * Given the first two numbers __a and __b of arbitrarily many evenly spaced + * numbers, pick the 0-based __index'th value. + * + * Always prefer this over _PICK() if the numbers are evenly spaced. + */ +#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) + +/* + * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. + * + * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. + */ +#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) + +#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) +#define _MASKED_FIELD(mask, value) ({ \ + if (__builtin_constant_p(mask)) \ + BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ + if (__builtin_constant_p(value)) \ + BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ + if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ + BUILD_BUG_ON_MSG((value) & ~(mask), \ + "Incorrect value for mask"); \ + __MASKED_FIELD(mask, value); }) +#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) +#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) + +typedef struct { + u32 reg; +} i915_reg_t; + +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) + +#define INVALID_MMIO_REG _MMIO(0) + +static inline u32 i915_mmio_reg_offset(i915_reg_t reg) +{ + return reg.reg; +} + +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) +{ + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); +} + +static inline bool i915_mmio_reg_valid(i915_reg_t reg) +{ + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); +} + +#endif diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index e06b35b844a0..7660b21c37bf 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -25,6 +25,7 @@ #include <asm/iosf_mbi.h> #include "i915_drv.h" +#include "intel_reg.h" #include "intel_sideband.h" /* diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9e583f13a9e4..144a10fd8614 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -28,6 +28,7 @@ #include "i915_trace.h" #include "i915_vgpu.h" #include "intel_pm.h" +#include "intel_reg.h" #define FORCEWAKE_ACK_TIMEOUT_MS 50 #define GT_FIFO_TIMEOUT_MS 10 diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 414fc2cb0459..fb500c2a4966 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -30,7 +30,7 @@ #include <linux/hrtimer.h> #include <linux/io-64-nonatomic-lo-hi.h> -#include "i915_reg.h" +#include "intel_reg_types.h" struct drm_i915_private; struct intel_runtime_pm;
With the introduction of display uncore, we want to categorize registers between display and non-display. To help us getting it right, it will be useful to move the display registers to a new file that can be used without including i915_reg.h. To allow that, move all the basic register type definitions and helpers to intel_reg_types.h and include that instead of i915_reg.h from header files in the driver. We'll then be able to replace i915_reg.h with the new display-only header in display files and make sure the registers are correctly compartmentalized. While at it, rename i915_reg.h to intel_reg.h to better indicate that it contains HW defs. v2: use intel_* prefix for register files (Michal) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> --- Documentation/gpu/i915.rst | 4 +- drivers/gpu/drm/i915/display/dvo_ns2501.c | 2 +- drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_audio.c | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 1 + drivers/gpu/drm/i915/display/intel_cdclk.c | 1 + drivers/gpu/drm/i915/display/intel_color.c | 1 + .../gpu/drm/i915/display/intel_combo_phy.c | 1 + drivers/gpu/drm/i915/display/intel_crt.c | 1 + drivers/gpu/drm/i915/display/intel_crt.h | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_power.c | 1 + .../drm/i915/display/intel_display_power.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_dp.h | 2 +- .../drm/i915/display/intel_dp_link_training.c | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 + drivers/gpu/drm/i915/display/intel_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 + drivers/gpu/drm/i915/display/intel_dvo.c | 1 + drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + .../drm/i915/display/intel_fifo_underrun.c | 1 + drivers/gpu/drm/i915/display/intel_gmbus.c | 1 + drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.h | 2 +- .../gpu/drm/i915/display/intel_lpe_audio.c | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.c | 1 + drivers/gpu/drm/i915/display/intel_lvds.h | 2 +- drivers/gpu/drm/i915/display/intel_opregion.c | 1 + drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 1 + drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 1 + drivers/gpu/drm/i915/display/intel_tc.c | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 + .../drm/i915/gem/selftests/i915_gem_context.c | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 2 +- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + drivers/gpu/drm/i915/gt/intel_mocs.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 1 + drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + .../gpu/drm/i915/gt/intel_workarounds_types.h | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +- drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 1 + drivers/gpu/drm/i915/gvt/edid.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/gtt.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/gvt/interrupt.c | 1 + drivers/gpu/drm/i915/gvt/mmio.c | 1 + drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + drivers/gpu/drm/i915/gvt/scheduler.c | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_gem_fence_reg.c | 1 + drivers/gpu/drm/i915/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_irq.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 1 + drivers/gpu/drm/i915/i915_suspend.c | 2 +- drivers/gpu/drm/i915/i915_sysfs.c | 1 + drivers/gpu/drm/i915/intel_csr.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + drivers/gpu/drm/i915/intel_pm.h | 2 +- .../gpu/drm/i915/{i915_reg.h => intel_reg.h} | 210 +---------------- drivers/gpu/drm/i915/intel_reg_types.h | 213 ++++++++++++++++++ drivers/gpu/drm/i915/intel_sideband.c | 1 + drivers/gpu/drm/i915/intel_uncore.c | 1 + drivers/gpu/drm/i915/intel_uncore.h | 2 +- 107 files changed, 324 insertions(+), 229 deletions(-) rename drivers/gpu/drm/i915/{i915_reg.h => intel_reg.h} (98%) create mode 100644 drivers/gpu/drm/i915/intel_reg_types.h