diff mbox series

[v2,07/11] pinctrl: mediatek: add mt6779 eint support

Message ID 1566206502-4347-8-git-send-email-mars.cheng@mediatek.com (mailing list archive)
State Not Applicable, archived
Headers show
Series Add basic SoC Support for Mediatek MT6779 SoC | expand

Commit Message

Mars Cheng Aug. 19, 2019, 9:21 a.m. UTC
add driver setting to support mt6779 eint

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
---
 drivers/pinctrl/mediatek/pinctrl-mt6779.c |    8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Sean Wang Aug. 22, 2019, 6:13 p.m. UTC | #1
On Mon, Aug 19, 2019 at 2:22 AM Mars Cheng <mars.cheng@mediatek.com> wrote:
>
> add driver setting to support mt6779 eint
>
> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>

Acked-by: Sean Wang <sean.wang@kernel.org>

> ---
>  drivers/pinctrl/mediatek/pinctrl-mt6779.c |    8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
> index 145bf22..49ff3cc 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
> @@ -731,11 +731,19 @@
>         "iocfg_rt", "iocfg_lt", "iocfg_tl",
>  };
>
> +static const struct mtk_eint_hw mt6779_eint_hw = {
> +       .port_mask = 7,
> +       .ports     = 6,
> +       .ap_num    = 209,
> +       .db_cnt    = 16,
> +};
> +
>  static const struct mtk_pin_soc mt6779_data = {
>         .reg_cal = mt6779_reg_cals,
>         .pins = mtk_pins_mt6779,
>         .npins = ARRAY_SIZE(mtk_pins_mt6779),
>         .ngrps = ARRAY_SIZE(mtk_pins_mt6779),
> +       .eint_hw = &mt6779_eint_hw,
>         .gpio_m = 0,
>         .ies_present = true,
>         .base_names = mt6779_pinctrl_register_base_names,
> --
> 1.7.9.5
>
diff mbox series

Patch

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf22..49ff3cc 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@ 
 	"iocfg_rt", "iocfg_lt", "iocfg_tl",
 };
 
+static const struct mtk_eint_hw mt6779_eint_hw = {
+	.port_mask = 7,
+	.ports     = 6,
+	.ap_num    = 209,
+	.db_cnt    = 16,
+};
+
 static const struct mtk_pin_soc mt6779_data = {
 	.reg_cal = mt6779_reg_cals,
 	.pins = mtk_pins_mt6779,
 	.npins = ARRAY_SIZE(mtk_pins_mt6779),
 	.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+	.eint_hw = &mt6779_eint_hw,
 	.gpio_m = 0,
 	.ies_present = true,
 	.base_names = mt6779_pinctrl_register_base_names,