| Message ID | 20190827191026.26175-10-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSB enablement. | expand |
So here is the documentation, this resolves atleast one review comment from me :) - Shashank On 8/28/2019 12:40 AM, Animesh Manna wrote: > Added docbook info regarding Display State Buffer(DSB) which > is added from gen12 onwards to batch submit display HW programming. > > v1: Initial version as RFC. > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > Documentation/gpu/i915.rst | 9 ++++ > drivers/gpu/drm/i915/display/intel_dsb.c | 68 ++++++++++++++++++++++++ > 2 files changed, 77 insertions(+) > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index 3415255ad3dc..38e31223a24c 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -246,6 +246,15 @@ Display PLLs > .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h > :internal: > > +Display State Buffer > +-------------------- > + > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c > + :doc: DSB > + > +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c > + :internal: > + > Memory Management and Command Submission > ======================================== > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c > index bc1734072f34..501ff7f5db8c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -9,6 +9,23 @@ > > #define DSB_BUF_SIZE (2 * PAGE_SIZE) > > +/** > + * DOC: DSB > + * > + * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory > + * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA > + * engine that can be programmed to download the DSB from memory. > + * It allows driver to batch submit display HW programming. This helps to > + * reduce loading time and CPU activity, thereby making the context switch > + * faster. DSB Support added from Gen12 Intel graphics based platform. > + * > + * DSB's can access only the pipe, plane, and transcoder Data Island Packet > + * registers. > + * > + * DSB HW can support only register writes (both indexed and direct MMIO > + * writes). There are no registers reads possible with DSB HW engine. > + */ > + > /* DSB opcodes. */ > #define DSB_OPCODE_SHIFT 24 > #define DSB_OPCODE_NOOP 0x0 > @@ -73,6 +90,17 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb) > return true; > } > > +/** > + * intel_dsb_get() - Allocate dsb context and return a dsb instance. > + * @crtc: intel_crtc structure to get pipe info. > + * > + * This function will give handle of the DSB instance which > + * user want to operate on. > + * > + * Return : address of Intel_dsb instance requested for. > + * In failure case, the dsb instance will not have any command buffer. > + */ > + > struct intel_dsb * > intel_dsb_get(struct intel_crtc *crtc) > { > @@ -124,6 +152,14 @@ intel_dsb_get(struct intel_crtc *crtc) > return dsb; > } > > +/** > + * intel_dsb_put() - To destroy DSB context. > + * @dsb: intel_dsb structure. > + * > + * This function is used to destroy the dsb-context by doing unpin > + * and release the vma object. > + */ > + > void intel_dsb_put(struct intel_dsb *dsb) > { > struct intel_crtc *crtc; > @@ -146,6 +182,19 @@ void intel_dsb_put(struct intel_dsb *dsb) > } > } > > +/** > + * intel_dsb_indexed_reg_write() -Write to the dsb context for auto > + * increment register. > + * @dsb: intel_dsb structure. > + * @reg: register address. > + * @val: value. > + * > + * This function is used for auto-increment register and intel_dsb_reg_write() > + * is used for normal register. During command buffer overflow, a warning > + * is thrown and rest all erroneous condition register programming is done > + * through mmio write. > + */ > + > void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, > u32 val) > { > @@ -193,6 +242,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, > buf[dsb->free_pos] = 0; > } > > +/** > + * intel_dsb_reg_write() -Write to the dsb context for normal > + * register. > + * @dsb: intel_dsb structure. > + * @reg: register address. > + * @val: value. > + * > + * This function is used for writing register-value pair in command > + * buffer of DSB. During command buffer overflow, a warning > + * is thrown and rest all erroneous condition register programming is done > + * through mmio write. > + */ > void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) > { > struct intel_crtc *crtc = dsb->crtc; > @@ -215,6 +276,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) > i915_mmio_reg_offset(reg); > } > > +/** > + * intel_dsb_commit() - Trigger workload execution of DSB. > + * @dsb: intel_dsb structure. > + * > + * This function is used to do actual write to hardware using DSB. > + * On errors, fall back to MMIO. Also this function help to reset the context. > + */ > void intel_dsb_commit(struct intel_dsb *dsb) > { > struct intel_crtc *crtc = dsb->crtc;
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 3415255ad3dc..38e31223a24c 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -246,6 +246,15 @@ Display PLLs .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h :internal: +Display State Buffer +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :doc: DSB + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :internal: + Memory Management and Command Submission ======================================== diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index bc1734072f34..501ff7f5db8c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -9,6 +9,23 @@ #define DSB_BUF_SIZE (2 * PAGE_SIZE) +/** + * DOC: DSB + * + * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory + * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA + * engine that can be programmed to download the DSB from memory. + * It allows driver to batch submit display HW programming. This helps to + * reduce loading time and CPU activity, thereby making the context switch + * faster. DSB Support added from Gen12 Intel graphics based platform. + * + * DSB's can access only the pipe, plane, and transcoder Data Island Packet + * registers. + * + * DSB HW can support only register writes (both indexed and direct MMIO + * writes). There are no registers reads possible with DSB HW engine. + */ + /* DSB opcodes. */ #define DSB_OPCODE_SHIFT 24 #define DSB_OPCODE_NOOP 0x0 @@ -73,6 +90,17 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb) return true; } +/** + * intel_dsb_get() - Allocate dsb context and return a dsb instance. + * @crtc: intel_crtc structure to get pipe info. + * + * This function will give handle of the DSB instance which + * user want to operate on. + * + * Return : address of Intel_dsb instance requested for. + * In failure case, the dsb instance will not have any command buffer. + */ + struct intel_dsb * intel_dsb_get(struct intel_crtc *crtc) { @@ -124,6 +152,14 @@ intel_dsb_get(struct intel_crtc *crtc) return dsb; } +/** + * intel_dsb_put() - To destroy DSB context. + * @dsb: intel_dsb structure. + * + * This function is used to destroy the dsb-context by doing unpin + * and release the vma object. + */ + void intel_dsb_put(struct intel_dsb *dsb) { struct intel_crtc *crtc; @@ -146,6 +182,19 @@ void intel_dsb_put(struct intel_dsb *dsb) } } +/** + * intel_dsb_indexed_reg_write() -Write to the dsb context for auto + * increment register. + * @dsb: intel_dsb structure. + * @reg: register address. + * @val: value. + * + * This function is used for auto-increment register and intel_dsb_reg_write() + * is used for normal register. During command buffer overflow, a warning + * is thrown and rest all erroneous condition register programming is done + * through mmio write. + */ + void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) { @@ -193,6 +242,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, buf[dsb->free_pos] = 0; } +/** + * intel_dsb_reg_write() -Write to the dsb context for normal + * register. + * @dsb: intel_dsb structure. + * @reg: register address. + * @val: value. + * + * This function is used for writing register-value pair in command + * buffer of DSB. During command buffer overflow, a warning + * is thrown and rest all erroneous condition register programming is done + * through mmio write. + */ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) { struct intel_crtc *crtc = dsb->crtc; @@ -215,6 +276,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) i915_mmio_reg_offset(reg); } +/** + * intel_dsb_commit() - Trigger workload execution of DSB. + * @dsb: intel_dsb structure. + * + * This function is used to do actual write to hardware using DSB. + * On errors, fall back to MMIO. Also this function help to reset the context. + */ void intel_dsb_commit(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc;