| Message ID | 20190828082150.42194-2-swboyd@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | tpm: Add driver for cr50 | expand |
On Wed, Aug 28, 2019 at 01:21:47AM -0700, Stephen Boyd wrote: > From: Andrey Pronin <apronin@chromium.org> > > Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 > firmware. > > Cc: Andrey Pronin <apronin@chromium.org> > Cc: Duncan Laurie <dlaurie@chromium.org> > Cc: Jason Gunthorpe <jgg@ziepe.ca> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Cc: Guenter Roeck <groeck@chromium.org> > Cc: Alexander Steffen <Alexander.Steffen@infineon.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Signed-off-by: Andrey Pronin <apronin@chromium.org> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Stephen Boyd <swboyd@chromium.org> > --- > .../bindings/security/tpm/google,cr50.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 Documentation/devicetree/bindings/security/tpm/google,cr50.txt > > diff --git a/Documentation/devicetree/bindings/security/tpm/google,cr50.txt b/Documentation/devicetree/bindings/security/tpm/google,cr50.txt > new file mode 100644 > index 000000000000..cd69c2efdd37 > --- /dev/null > +++ b/Documentation/devicetree/bindings/security/tpm/google,cr50.txt > @@ -0,0 +1,19 @@ > +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. > + > +H1 Secure Microcontroller running Cr50 firmware provides several > +functions, including TPM-like functionality. It communicates over > +SPI using the FIFO protocol described in the PTP Spec, section 6. > + > +Required properties: > +- compatible: Should be "google,cr50". > +- spi-max-frequency: Maximum SPI frequency. > + > +Example: > + > +&spi0 { > + tpm@0 { > + compatible = "google,cr50"; > + reg = <0>; > + spi-max-frequency = <800000>; > + }; > +}; > -- > Sent by a computer through tubes > Acked-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> /Jarkko
diff --git a/Documentation/devicetree/bindings/security/tpm/google,cr50.txt b/Documentation/devicetree/bindings/security/tpm/google,cr50.txt new file mode 100644 index 000000000000..cd69c2efdd37 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/google,cr50.txt @@ -0,0 +1,19 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + tpm@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +};