| Message ID | 20190828172850.19871-2-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform | expand |
On Wed, Aug 28, 2019 at 10:58:45PM +0530, Vidya Sagar wrote: > Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin > configuration information of a particular PCIe controller. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V3: > * None > > V2: > * None > > .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > index 674e5adb2895..0ac1b867ac24 100644 > --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > @@ -83,6 +83,11 @@ Required properties: > - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals > > Optional properties: > +- pinctrl-names: A list of pinctrl state names. > + It is mandatory for C5 controller and optional for other controllers. > + - "default": Configures PCIe I/O for proper operation. > +- pinctrl-0: phandle for the 'default' state of pin configuration. > + It is mandatory for C5 controller and optional for other controllers. > - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt > - nvidia,update-fc-fixup: This is a boolean property and needs to be present to > improve performance when a platform is designed in such a way that it > @@ -120,6 +125,9 @@ Tegra194: > num-lanes = <8>; > linux,pci-domain = <0>; > > + pinctrl-names = "default"; > + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; > + > clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; > clock-names = "core"; > > -- > 2.17.1 >
On Wed, Aug 28, 2019 at 10:58:45PM +0530, Vidya Sagar wrote: > Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin > configuration information of a particular PCIe controller. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > V3: > * None > > V2: > * None > > .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ > 1 file changed, 8 insertions(+) Acked-by: Thierry Reding <treding@nvidia.com>
On Wed, 28 Aug 2019 22:58:45 +0530, Vidya Sagar wrote: > Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin > configuration information of a particular PCIe controller. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > V3: > * None > > V2: > * None > > .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ > 1 file changed, 8 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index 674e5adb2895..0ac1b867ac24 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -83,6 +83,11 @@ Required properties: - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals Optional properties: +- pinctrl-names: A list of pinctrl state names. + It is mandatory for C5 controller and optional for other controllers. + - "default": Configures PCIe I/O for proper operation. +- pinctrl-0: phandle for the 'default' state of pin configuration. + It is mandatory for C5 controller and optional for other controllers. - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt - nvidia,update-fc-fixup: This is a boolean property and needs to be present to improve performance when a platform is designed in such a way that it @@ -120,6 +125,9 @@ Tegra194: num-lanes = <8>; linux,pci-domain = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; clock-names = "core";
Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin configuration information of a particular PCIe controller. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V3: * None V2: * None .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ 1 file changed, 8 insertions(+)