| Message ID | 20190811104008.53372-1-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Support dsi for mt8183 | expand |
Hi, Jitao: For this series, applied to mediatek-drm-next-5.5 [1], and I break "[v6,2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701" into two patches, thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK On Sun, 2019-08-11 at 18:40 +0800, Jitao Shi wrote: > Change since v5: > - fine tune dphy timing. > > Change since v4: > - move mipi_dsi_host_unregiter() to .remove() > - fine tune add frame size control coding style > - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL > - use div_u64 when 8000000000ULL / dsi->data_rate. > > Changes since v3 > - add one more 'tab' for bitwise define. > - add Tested-by: Ryan Case <ryandcase@chromium.org> > and Reviewed-by: CK Hu <ck.hu@mediatek.com>. > - remove compare da_hs_zero to da_hs_prepare. > > Changes since v2: > - change the video timing calc method > - fine the dsi and mipitx init sequence > - fine tune commit msg > > Changes since v1: > - separate frame size and reg commit control independent patches. > - fix some return values in probe > - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" > > Jitao Shi (7): > drm/mediatek: move mipi_dsi_host_register to probe > drm/mediatek: fixes CMDQ reg address of mt8173 is different with > mt2701 > drm/mediatek: add dsi reg commit disable control > drm/mediatek: add frame size control > drm/mediatek: add mt8183 dsi driver support > drm/mediatek: change the dsi phytiming calculate method > drm: mediatek: adjust dsi and mipi_tx probe sequence > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- > drivers/gpu/drm/mediatek/mtk_dsi.c | 224 ++++++++++++++++++------- > 2 files changed, 161 insertions(+), 65 deletions(-) >
Hello, I somehow fail to see how this is relevant for the linux-pwm list. Did you add this list to the recipents by accident, or is there something I missed? Best regards Uwe
Change since v5: - fine tune dphy timing. Change since v4: - move mipi_dsi_host_unregiter() to .remove() - fine tune add frame size control coding style - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL - use div_u64 when 8000000000ULL / dsi->data_rate. Changes since v3 - add one more 'tab' for bitwise define. - add Tested-by: Ryan Case <ryandcase@chromium.org> and Reviewed-by: CK Hu <ck.hu@mediatek.com>. - remove compare da_hs_zero to da_hs_prepare. Changes since v2: - change the video timing calc method - fine the dsi and mipitx init sequence - fine tune commit msg Changes since v1: - separate frame size and reg commit control independent patches. - fix some return values in probe - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" Jitao Shi (7): drm/mediatek: move mipi_dsi_host_register to probe drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 drm/mediatek: add dsi reg commit disable control drm/mediatek: add frame size control drm/mediatek: add mt8183 dsi driver support drm/mediatek: change the dsi phytiming calculate method drm: mediatek: adjust dsi and mipi_tx probe sequence drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 224 ++++++++++++++++++------- 2 files changed, 161 insertions(+), 65 deletions(-)