| Message ID | 1567090254-15566-33-git-send-email-yongqiang.niu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add drm support for MT8183 | expand |
Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++++++++++++++++++++ > 5 files changed, 161 insertions(+), 1 deletion(-) > [snip] > @@ -613,6 +658,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-display", This should be "mediatek,mt8183-mmsys". Regards, CK > + .data = &mt8183_mmsys_driver_data}, > { } > }; >
Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++++++++++++++++++++ > 5 files changed, 161 insertions(+), 1 deletion(-) > [snip] > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 9a6f0a2..24945fe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -62,6 +62,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); I think the fifo size part should be an independent patch because it has no strong relation with MT8183. > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); > } > @@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + > + priv->fifo_size *= SZ_1K; > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > @@ -328,11 +347,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > [snip] > @@ -514,6 +558,7 @@ static int mtk_drm_probe(struct platform_device *pdev) > */ > if (comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_OVL || > + comp_type == MTK_DISP_OVL_2L || I think this should be squashed into "[v5,15/32] drm/mediatek: add commponent OVL_2L0'. Regards, CK > comp_type == MTK_DISP_RDMA || > comp_type == MTK_DSI || > comp_type == MTK_DPI) {
On 29/08/2019 16:50, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> After a long time the mmsys problem is fixed [1], so pelase rebase your series on linux-next and resend. Thanks a lot! [1] https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=1f9adbc72824ff07bbffd776d8b51f91f5a82c18 > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++++++++++++- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++++++++++++++++++++ > 5 files changed, 161 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 53f3883..94c80c2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -373,11 +373,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = &mt8173_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = &mt8183_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = &mt8183_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 9a6f0a2..24945fe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -62,6 +62,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); > } > @@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + > + priv->fifo_size *= SZ_1K; > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > @@ -328,11 +347,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = &mt8173_rdma_driver_data}, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = &mt8183_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 6a7cb15..9be6eae 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -33,19 +33,31 @@ > #define DISP_REG_CONFIG_DSI_SEL 0x050 > #define DISP_REG_CONFIG_DPI_SEL 0x064 > > +#define MT8183_DISP_OVL0_MOUT_EN 0xf00 > #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04 > #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08 > #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c > #define MT8183_DISP_PATH0_SEL_IN 0xf24 > +#define MT8183_DISP_DSI0_SEL_IN 0xf2c > +#define MT8183_DISP_DPI0_SEL_IN 0xf30 > +#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50 > +#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54 > > #define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) > #define OVL1_2L_MOUT_EN_RDMA1 BIT(4) > #define DITHER0_MOUT_IN_DSI0 BIT(0) > #define DISP_PATH0_SEL_IN_OVL0_2L 0x1 > #define DSI0_SEL_IN_RDMA0 0x1 > +#define MT8183_DSI0_SEL_IN_RDMA1 0x3 > +#define MT8183_DPI0_SEL_IN_RDMA0 0x1 > +#define MT8183_DPI0_SEL_IN_RDMA1 0x2 > +#define MT8183_RDMA0_SOUT_COLOR0 0x1 > +#define MT8183_RDMA1_SOUT_DSI0 0x1 > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -56,6 +68,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -105,6 +129,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > #define OVL0_MOUT_EN_COLOR0 0x1 > #define OD_MOUT_EN_RDMA0 0x1 > #define OD1_MOUT_EN_RDMA1 BIT(16) > @@ -240,6 +268,20 @@ struct mtk_mmsys_reg_data { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -250,6 +292,12 @@ struct mtk_mmsys_reg_data { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -271,6 +319,13 @@ struct mtk_mmsys_reg_data { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > + .mutex_mod = mt8183_mutex_mod, > + .mutex_sof = mt8183_mutex_sof, > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > +}; > + > const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = { > .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, > .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL, > @@ -287,6 +342,18 @@ struct mtk_mmsys_reg_data { > .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1, > }; > > +const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data = { > + .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, > + .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, > + .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, > + .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, > + .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, > + .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, > + .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, > + .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, > + .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, > +}; > + > static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > @@ -734,6 +801,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > .data = &mt2712_ddp_driver_data}, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = &mt8173_ddp_driver_data}, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = &mt8183_ddp_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > index c55cc63..b74d8b9 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h > @@ -15,6 +15,7 @@ > > extern const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data; > extern const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data; > +extern const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data; > void mtk_ddp_add_comp_to_path(void __iomem *config_regs, > const struct mtk_mmsys_reg_data *reg_data, > enum mtk_ddp_comp_id cur, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 2471ce9..a4346fe 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -184,6 +184,24 @@ static int mtk_atomic_commit(struct drm_device *drm, > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -211,6 +229,14 @@ static int mtk_atomic_commit(struct drm_device *drm, > .reg_data = &mt8173_mmsys_reg_data, > }; > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > + .main_path = mt8183_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > + .ext_path = mt8183_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > + .reg_data = &mt8183_mmsys_reg_data, > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -409,12 +435,22 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma1", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > @@ -423,22 +459,30 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8183-disp-dither", > + .data = (void *)MTK_DISP_DITHER }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8183-dsi", > + .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt2701-dpi", > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8173-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8183-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > @@ -514,6 +558,7 @@ static int mtk_drm_probe(struct platform_device *pdev) > */ > if (comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_OVL || > + comp_type == MTK_DISP_OVL_2L || > comp_type == MTK_DISP_RDMA || > comp_type == MTK_DSI || > comp_type == MTK_DPI) { > @@ -613,6 +658,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-display", > + .data = &mt8183_mmsys_driver_data}, > { } > }; > >
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 53f3883..94c80c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -373,11 +373,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 9a6f0a2..24945fe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -62,6 +62,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; const struct mtk_disp_rdma_data *data; + u32 fifo_size; }; static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) @@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + u32 rdma_fifo_size; rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); } @@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma_fifo_size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + + priv->fifo_size *= SZ_1K; + } + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { @@ -328,11 +347,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 6a7cb15..9be6eae 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -33,19 +33,31 @@ #define DISP_REG_CONFIG_DSI_SEL 0x050 #define DISP_REG_CONFIG_DPI_SEL 0x064 +#define MT8183_DISP_OVL0_MOUT_EN 0xf00 #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04 #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08 #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c #define MT8183_DISP_PATH0_SEL_IN 0xf24 +#define MT8183_DISP_DSI0_SEL_IN 0xf2c +#define MT8183_DISP_DPI0_SEL_IN 0xf30 +#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54 #define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) #define OVL1_2L_MOUT_EN_RDMA1 BIT(4) #define DITHER0_MOUT_IN_DSI0 BIT(0) #define DISP_PATH0_SEL_IN_OVL0_2L 0x1 #define DSI0_SEL_IN_RDMA0 0x1 +#define MT8183_DSI0_SEL_IN_RDMA1 0x3 +#define MT8183_DPI0_SEL_IN_RDMA0 0x1 +#define MT8183_DPI0_SEL_IN_RDMA1 0x2 +#define MT8183_RDMA0_SOUT_COLOR0 0x1 +#define MT8183_RDMA1_SOUT_DSI0 0x1 #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -56,6 +68,18 @@ #define INT_MUTEX BIT(1) +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -105,6 +129,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6 +#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) + #define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 #define OD1_MOUT_EN_RDMA1 BIT(16) @@ -240,6 +268,20 @@ struct mtk_mmsys_reg_data { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -250,6 +292,12 @@ struct mtk_mmsys_reg_data { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -271,6 +319,13 @@ struct mtk_mmsys_reg_data { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, }; +static const struct mtk_ddp_data mt8183_ddp_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, +}; + const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = { .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL, @@ -287,6 +342,18 @@ struct mtk_mmsys_reg_data { .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1, }; +const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data = { + .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, + .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, + .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, + .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, + .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, + .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, + .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, + .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, + .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, +}; + static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, @@ -734,6 +801,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h index c55cc63..b74d8b9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h @@ -15,6 +15,7 @@ extern const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data; extern const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data; +extern const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data; void mtk_ddp_add_comp_to_path(void __iomem *config_regs, const struct mtk_mmsys_reg_data *reg_data, enum mtk_ddp_comp_id cur, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 2471ce9..a4346fe 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -184,6 +184,24 @@ static int mtk_atomic_commit(struct drm_device *drm, DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -211,6 +229,14 @@ static int mtk_atomic_commit(struct drm_device *drm, .reg_data = &mt8173_mmsys_reg_data, }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), + .reg_data = &mt8183_mmsys_reg_data, +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -409,12 +435,22 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma1", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -423,22 +459,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -514,6 +558,7 @@ static int mtk_drm_probe(struct platform_device *pdev) */ if (comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_OVL || + comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_RDMA || comp_type == MTK_DSI || comp_type == MTK_DPI) { @@ -613,6 +658,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-display", + .data = &mt8183_mmsys_driver_data}, { } };