| Message ID | 29e895912c2f4989937fa33d59e55dd9@zhaoxin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/4] x86/mce: Add Zhaoxin MCE support | expand |
On Mon, 9 Sep 2019, kbuild test robot <lkp@intel.com> wrote: >Hi Tony, > >I love your patch! Yet something to improve: Glad to hear, thanks. > >[auto build test ERROR on linus/master] >[cannot apply to v5.3-rc8 next-20190904] >[if your patch is applied to the wrong git tree, please drop us a note to help >improve the system] > >url: >https://github.com/0day-ci/linux/commits/Tony-W-Wang-oc/x86-mce-Add-Zhao >xin-MCE-support/20190909-190435 >config: i386-randconfig-b002-201936 (attached as .config) >compiler: gcc-7 (Debian 7.4.0-11) 7.4.0 >reproduce: > # save the attached .config to linux build tree > make ARCH=i386 > >If you fix the issue, kindly add following tag >Reported-by: kbuild test robot <lkp@intel.com> > >All errors (new ones prefixed by >>): > >>> arch/x86/kernel/cpu/mce/core.c:1780:6: error: redefinition of >'mce_zhaoxin_feature_init' > void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) > ^~~~~~~~~~~~~~~~~~~~~~~~ > In file included from arch/x86/kernel/cpu/mce/core.c:50:0: > arch/x86/include/asm/mce.h:356:20: note: previous definition of >'mce_zhaoxin_feature_init' was here > static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { } > ^~~~~~~~~~~~~~~~~~~~~~~~ > >vim +/mce_zhaoxin_feature_init +1780 arch/x86/kernel/cpu/mce/core.c > > 1779 >> 1780 void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) > 1781 { > 1782 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); > 1783 > 1784 /* > 1785 * These CPUs bank8 SVAD error may be triggered unexpected >when > 1786 * bringup virtual machine. it is not hardware bug. Always disable > 1787 * bank8 SVAD error by default. > 1788 */ > 1789 if ((c->x86 == 6 && c->x86_model == 0x19 && > 1790 (c->x86_stepping > 3 && c->x86_stepping < 8)) || > 1791 (c->x86 == 6 && c->x86_model == 0x1f) || > 1792 (c->x86 == 7 && c->x86_model == 0x1b)) { > 1793 if (this_cpu_read(mce_num_banks) > 8) > 1794 mce_banks[8].ctl = 0; > 1795 } > 1796 > 1797 intel_init_cmci(); > 1798 mce_adjust_timer = cmci_intel_adjust_timer; > 1799 } > 1800 > Will fix this issue in V2. >--- >0-DAY kernel test infrastructure Open Source Technology >Center >https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index dc2d4b2..0986a11 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -350,4 +350,10 @@ umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } +#ifdef CONFIG_CPU_SUP_ZHAOXIN +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); +#else +static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { } +#endif + #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 3f878f6..a3b07ca 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1777,6 +1777,27 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) } } +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + + /* + * These CPUs bank8 SVAD error may be triggered unexpected when + * bringup virtual machine. it is not hardware bug. Always disable + * bank8 SVAD error by default. + */ + if ((c->x86 == 6 && c->x86_model == 0x19 && + (c->x86_stepping > 3 && c->x86_stepping < 8)) || + (c->x86 == 6 && c->x86_model == 0x1f) || + (c->x86 == 7 && c->x86_model == 0x1b)) { + if (this_cpu_read(mce_num_banks) > 8) + mce_banks[8].ctl = 0; + } + + intel_init_cmci(); + mce_adjust_timer = cmci_intel_adjust_timer; +} + static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { switch (c->x86_vendor) { @@ -1798,6 +1819,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_centaur_feature_init(c); break; + case X86_VENDOR_ZHAOXIN: + mce_zhaoxin_feature_init(c); + break; + default: break; } diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index eee4b12..b49cba7 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -85,7 +85,8 @@ static int cmci_supported(int *banks) * initialization is vendor keyed and this * makes sure none of the backdoors are entered otherwise. */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) return 0; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0;
All Zhaoxin newer CPUs support CMCI that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin CMCI in mce/core.c and mce/intel.c. Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> --- arch/x86/include/asm/mce.h | 6 ++++++ arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/intel.c | 3 ++- 3 files changed, 33 insertions(+), 1 deletion(-)