| Message ID | 20190911133129.27466-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk | expand |
On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > On tgl/bxt/glk the cdclk bypass frequency depends on the PLL > reference clock. So let's read out the ref clock before we > try to compute the bypass clock. > > Cc: Matt Roper <matthew.d.roper@intel.com> > Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout") > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 618a93bad0a8..6b75d2a91cd9 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > u32 divider; > int div; > > + bxt_de_pll_readout(dev_priv, cdclk_state); > + > if (INTEL_GEN(dev_priv) >= 12) > cdclk_state->bypass = cdclk_state->ref / 2; > else if (INTEL_GEN(dev_priv) >= 11) > @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > else > cdclk_state->bypass = cdclk_state->ref; > > - bxt_de_pll_readout(dev_priv, cdclk_state); > if (cdclk_state->vco == 0) { > cdclk_state->cdclk = cdclk_state->bypass; > goto out; > -- > 2.21.0 >
Quoting Patchwork (2019-09-12 10:36:49) > == Series Details == > > Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk (rev2) > URL : https://patchwork.freedesktop.org/series/66537/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6875 -> Patchwork_14374 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14374/ Ignorance is bliss. Pushed, so the onus falls back onto the GEM failures. Thanks for the fixes, -Chris
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 618a93bad0a8..6b75d2a91cd9 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, u32 divider; int div; + bxt_de_pll_readout(dev_priv, cdclk_state); + if (INTEL_GEN(dev_priv) >= 12) cdclk_state->bypass = cdclk_state->ref / 2; else if (INTEL_GEN(dev_priv) >= 11) @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, else cdclk_state->bypass = cdclk_state->ref; - bxt_de_pll_readout(dev_priv, cdclk_state); if (cdclk_state->vco == 0) { cdclk_state->cdclk = cdclk_state->bypass; goto out;