| Message ID | 20190912015104.10737-1-ankur.tyagi@gallagher.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
On 12/09/2019 04:51, Ankur Tyagi wrote: > Sitara technical reference manual numbers GPIO from 0-3 whereas > in code GPIO are numbered from 1-4. > > Signed-off-by: Ankur Tyagi <ankur.tyagi@gallagher.com> Same comments as for patch #1, causing compile breakage + bisect issues. Also, next time when posting, can you send patches as a proper series so individual patches get sorted in the recipient mailboxes automatically? Otherwise it is easy to lose patches if they are not grouped properly. git send-email tool does this for you automatically for example. -Tero > --- > drivers/clk/ti/clk-33xx.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c > index a360d3109555..d67f1f6bbec0 100644 > --- a/drivers/clk/ti/clk-33xx.c > +++ b/drivers/clk/ti/clk-33xx.c > @@ -28,17 +28,17 @@ static const char * const am3_gpio1_dbclk_parents[] __initconst = { > NULL, > }; > > -static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { > +static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > { 0 }, > }; > > -static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { > +static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > { 0 }, > }; > > -static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { > +static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > { 0 }, > }; > @@ -61,9 +61,9 @@ static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = > { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, > { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, > { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, > + { AM3_L4LS_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, > { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, > { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, > - { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, > { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, > { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, > { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, > @@ -131,14 +131,14 @@ static const char * const am3_gpio0_dbclk_parents[] __initconst = { > NULL, > }; > > -static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { > +static const struct omap_clkctrl_bit_data am3_gpio0_bit_data[] __initconst = { > { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, > { 0 }, > }; > > static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { > { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, > - { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, > + { AM3_L4_WKUP_GPIO0_CLKCTRL, am3_gpio0_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, > { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, > { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, > { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, > -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> -----Original Message----- > From: Tero Kristo <t-kristo@ti.com> > Sent: Thursday, 12 September 2019 7:43 PM > To: Ankur Tyagi <Ankur.Tyagi@gallagher.com>; mturquette@baylibre.com; > sboyd@kernel.org > Cc: linux-omap@vger.kernel.org; Ondrej Pohl <Ondrej.Pohl@gallagher.com> > Subject: Re: [PATCH 2/2] clk: ti: clk-33xx.c: Update GPIO number as per > datasheet > > On 12/09/2019 04:51, Ankur Tyagi wrote: > > Sitara technical reference manual numbers GPIO from 0-3 whereas in > > code GPIO are numbered from 1-4. > > > > Signed-off-by: Ankur Tyagi <ankur.tyagi@gallagher.com> > > Same comments as for patch #1, causing compile breakage + bisect issues. > > Also, next time when posting, can you send patches as a proper series so > individual patches get sorted in the recipient mailboxes automatically? > Otherwise it is easy to lose patches if they are not grouped properly. > git send-email tool does this for you automatically for example. > > -Tero I wasn't sure about sending DT fix in this mailing list but I guess it make sense to send series in same list to avoid confusion. Thanks Ankur > > > --- > > drivers/clk/ti/clk-33xx.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c > > index a360d3109555..d67f1f6bbec0 100644 > > --- a/drivers/clk/ti/clk-33xx.c > > +++ b/drivers/clk/ti/clk-33xx.c > > @@ -28,17 +28,17 @@ static const char * const > am3_gpio1_dbclk_parents[] __initconst = { > > NULL, > > }; > > > > -static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] > > __initconst = { > > +static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] > > +__initconst = { > > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > > { 0 }, > > }; > > > > -static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] > > __initconst = { > > +static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] > > +__initconst = { > > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > > { 0 }, > > }; > > > > -static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] > > __initconst = { > > +static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] > > +__initconst = { > > { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, > > { 0 }, > > }; > > @@ -61,9 +61,9 @@ static const struct omap_clkctrl_reg_data > am3_l4ls_clkctrl_regs[] __initconst = > > { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, > > { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, > > { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, > > +{ AM3_L4LS_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, > > +"l4ls_gclk" }, > > { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, > "l4ls_gclk" }, > > { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, > "l4ls_gclk" }, > > -{ AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, > "l4ls_gclk" }, > > { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, > > { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, > > { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, > @@ > > -131,14 +131,14 @@ static const char * const am3_gpio0_dbclk_parents[] > __initconst = { > > NULL, > > }; > > > > -static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] > > __initconst = { > > +static const struct omap_clkctrl_bit_data am3_gpio0_bit_data[] > > +__initconst = { > > { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, > > { 0 }, > > }; > > > > static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] > __initconst = { > > { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, > "dpll_core_m4_div2_ck" }, > > -{ AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, > CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, > > +{ AM3_L4_WKUP_GPIO0_CLKCTRL, am3_gpio0_bit_data, > CLKF_SW_SUP, > > +"dpll_core_m4_div2_ck" }, > > { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, > "dpll_core_m4_div2_ck" }, > > { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, > "dpll_per_m2_div4_wkupdm_ck" }, > > { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, > > "dpll_per_m2_div4_wkupdm_ck" }, > > > > -- > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y- > tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index a360d3109555..d67f1f6bbec0 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -28,17 +28,17 @@ static const char * const am3_gpio1_dbclk_parents[] __initconst = { NULL, }; -static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { +static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, { 0 }, }; -static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { +static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, { 0 }, }; -static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { +static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, { 0 }, }; @@ -61,9 +61,9 @@ static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, + { AM3_L4LS_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, @@ -131,14 +131,14 @@ static const char * const am3_gpio0_dbclk_parents[] __initconst = { NULL, }; -static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { +static const struct omap_clkctrl_bit_data am3_gpio0_bit_data[] __initconst = { { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, { 0 }, }; static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, - { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, + { AM3_L4_WKUP_GPIO0_CLKCTRL, am3_gpio0_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
Sitara technical reference manual numbers GPIO from 0-3 whereas in code GPIO are numbered from 1-4. Signed-off-by: Ankur Tyagi <ankur.tyagi@gallagher.com> --- drivers/clk/ti/clk-33xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)