| Message ID | 20190918104634.15216-5-s.nawrocki@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/9] ASoC: wm8994: Do not register inapplicable controls for WM1811 | expand |
On Wed, Sep 18, 2019 at 12:46:29PM +0200, Sylwester Nawrocki wrote: > As an intermediate step before covering the clocking subsystem > of the CODEC entirely by the clk API add handling of external CODEC's > master clocks in DAPM events when the AIFn clocks are sourced directly > from MCLKn; when FLLn are used we enable/disable respective MCLKn > before/after FLLn is enabled/disabled. > > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- > @@ -2260,8 +2321,28 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, > /* Clear any pending completion from a previous failure */ > try_wait_for_completion(&wm8994->fll_locked[id]); > > + switch (src) { > + case WM8994_FLL_SRC_MCLK1: > + mclk = control->mclk[0].clk; > + break; > + case WM8994_FLL_SRC_MCLK2: > + mclk = control->mclk[1].clk; > + break; > + default: > + mclk = NULL; > + } > + > /* Enable (with fractional mode if required) */ > if (freq_out) { > + if (mclk) { > + ret = clk_prepare_enable(mclk); > + if (ret < 0) { > + dev_err(component->dev, > + "Failed to enable MCLK for FLL%d\n", > + id + 1); > + return ret; > + } > + } > /* Enable VMID if we need it */ > if (!was_enabled) { > active_reference(component); > @@ -2315,6 +2396,8 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, > > active_dereference(component); > } > + if (mclk) > + clk_disable_unprepare(mclk); I don't think this works in the case of changing active FLLs. The driver looks like it allows changing the FLL configuration whilst the FLL is already active in which case it you would have two wm8994_set_fll calls enabling the FLL but only a single one disabling it. Resulting in the FLL being off but the MCLK being left enabled. Thanks, Charles
On 9/18/19 16:31, Charles Keepax wrote: >> @@ -2315,6 +2396,8 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, >> >> active_dereference(component); >> } >> + if (mclk) >> + clk_disable_unprepare(mclk); > > I don't think this works in the case of changing active FLLs. > The driver looks like it allows changing the FLL configuration > whilst the FLL is already active in which case it you would have > two wm8994_set_fll calls enabling the FLL but only a single one > disabling it. Resulting in the FLL being off but the MCLK being > left enabled. Indeed I missed this scenario, or rather assumed it won't be used. But since the driver allows reconfiguring active FLLs we should make sure such use case remains properly supported. What I came up so far as a fix is reading current FLL refclk source and if FLL was enabled with that source disabling refclk, before we change FLL configuration to new one. So we have clk_disable_unprepare(MCLK) more closely following FLL enable bit changes. I have tested it and it seems to work - something like below. Do you think it makes sense?
On Thu, Sep 19, 2019 at 01:58:35PM +0200, Sylwester Nawrocki wrote: > On 9/18/19 16:31, Charles Keepax wrote: > >> @@ -2315,6 +2396,8 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, > >> > >> active_dereference(component); > >> } > >> + if (mclk) > >> + clk_disable_unprepare(mclk); > > > > I don't think this works in the case of changing active FLLs. > > The driver looks like it allows changing the FLL configuration > > whilst the FLL is already active in which case it you would have > > two wm8994_set_fll calls enabling the FLL but only a single one > > disabling it. Resulting in the FLL being off but the MCLK being > > left enabled. > > Indeed I missed this scenario, or rather assumed it won't be used. > But since the driver allows reconfiguring active FLLs we should make > sure such use case remains properly supported. > > What I came up so far as a fix is reading current FLL refclk source and > if FLL was enabled with that source disabling refclk, before we change FLL > configuration to new one. So we have clk_disable_unprepare(MCLK) more > closely following FLL enable bit changes. I have tested it and it seems > to work - something like below. Do you think it makes sense? > Yeah I think that looks good, it is very similar to what we did on Arizona and I haven't found any problems with that yet :-) Thanks, Charles
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c index b6b0842ae1fc..bf02e8908d5a 100644 --- a/sound/soc/codecs/wm8994.c +++ b/sound/soc/codecs/wm8994.c @@ -1038,6 +1038,46 @@ static bool wm8994_check_class_w_digital(struct snd_soc_component *component) return true; } +static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable) +{ + struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); + struct wm8994 *control = wm8994->wm8994; + unsigned int offset, val, clk_idx; + int ret; + + if (aif) + offset = 4; + else + offset = 0; + + val = snd_soc_component_read32(component, WM8994_AIF1_CLOCKING_1 + offset); + val &= WM8994_AIF1CLK_SRC_MASK; + + switch (val) { + case 0: + clk_idx = WM8994_MCLK1; + break; + case 1: + clk_idx = WM8994_MCLK2; + break; + default: + return 0; + } + + if (enable) { + ret = clk_prepare_enable(control->mclk[clk_idx].clk); + if (ret < 0) { + dev_err(component->dev, "Failed to enable MCLK%d\n", + clk_idx); + return ret; + } + } else { + clk_disable_unprepare(control->mclk[clk_idx].clk); + } + + return 0; +} + static int aif1clk_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -1045,7 +1085,7 @@ static int aif1clk_ev(struct snd_soc_dapm_widget *w, struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); struct wm8994 *control = wm8994->wm8994; int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; - int i; + int ret, i; int dac; int adc; int val; @@ -1061,6 +1101,10 @@ static int aif1clk_ev(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: + ret = aif_mclk_set(component, 0, true); + if (ret < 0) + return ret; + /* Don't enable timeslot 2 if not in use */ if (wm8994->channels[0] <= 2) mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); @@ -1133,6 +1177,12 @@ static int aif1clk_ev(struct snd_soc_dapm_widget *w, break; } + switch (event) { + case SND_SOC_DAPM_POST_PMD: + aif_mclk_set(component, 0, false); + break; + } + return 0; } @@ -1140,13 +1190,17 @@ static int aif2clk_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); - int i; + int ret, i; int dac; int adc; int val; switch (event) { case SND_SOC_DAPM_PRE_PMU: + ret = aif_mclk_set(component, 1, true); + if (ret < 0) + return ret; + val = snd_soc_component_read32(component, WM8994_AIF2_CONTROL_1); if ((val & WM8994_AIF2ADCL_SRC) && (val & WM8994_AIF2ADCR_SRC)) @@ -1218,6 +1272,12 @@ static int aif2clk_ev(struct snd_soc_dapm_widget *w, break; } + switch (event) { + case SND_SOC_DAPM_POST_PMD: + aif_mclk_set(component, 1, false); + break; + } + return 0; } @@ -1623,10 +1683,10 @@ SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), @@ -2141,6 +2201,7 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, u16 reg, clk1, aif_reg, aif_src; unsigned long timeout; bool was_enabled; + struct clk *mclk; switch (id) { case WM8994_FLL1: @@ -2260,8 +2321,28 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, /* Clear any pending completion from a previous failure */ try_wait_for_completion(&wm8994->fll_locked[id]); + switch (src) { + case WM8994_FLL_SRC_MCLK1: + mclk = control->mclk[0].clk; + break; + case WM8994_FLL_SRC_MCLK2: + mclk = control->mclk[1].clk; + break; + default: + mclk = NULL; + } + /* Enable (with fractional mode if required) */ if (freq_out) { + if (mclk) { + ret = clk_prepare_enable(mclk); + if (ret < 0) { + dev_err(component->dev, + "Failed to enable MCLK for FLL%d\n", + id + 1); + return ret; + } + } /* Enable VMID if we need it */ if (!was_enabled) { active_reference(component); @@ -2315,6 +2396,8 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, active_dereference(component); } + if (mclk) + clk_disable_unprepare(mclk); } out:
As an intermediate step before covering the clocking subsystem of the CODEC entirely by the clk API add handling of external CODEC's master clocks in DAPM events when the AIFn clocks are sourced directly from MCLKn; when FLLn are used we enable/disable respective MCLKn before/after FLLn is enabled/disabled. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> --- sound/soc/codecs/wm8994.c | 91 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 87 insertions(+), 4 deletions(-)