Message ID | 20191008001318.219367-1-jonathan@fintelia.io (mailing list archive) |
---|---|
Headers | show |
Series | target/riscv: Expose "priv" register for GDB | expand |
The first paragraph seems to have gone missing. Repeated below: > This series adds a new "priv" virtual register that reports the current > privilege mode. This is helpful for debugging purposes because that information > is not actually available in any of the real CSRs. On Mon, Oct 7, 2019 at 8:15 PM Jonathan Behrens <jonathan@fintelia.io> wrote: > > The third patch in this series makes the priv virtual register writitable. I'm > not entirely sure this is a good idea, so I split it out into its own patch. In > particular, this change will conflict with the hypervisor extension work which > assumes that the privilege mode does not change in unexpected cases. > > As pointed out in a previous version of this series, GDB actually contains some > support already for the accessing the privilege mode via a virtual "priv" > register, including to convert the values into human readable forms: > > (gdb) info reg priv > priv 0x3 prv:3 [Machine] > > Changlog V3: > - Break patch into series > - Make priv a virtual register > > Changelog V2: > - Use PRV_H and PRV_S instead of integer literals > > Jonathan Behrens (3) > target/riscv: Tell gdbstub the correct number of CSRs > target/riscv: Expose priv register for GDB for reads > target/riscv: Make the priv register writable by GDB > > configure | 4 ++-- > gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++ > gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++ > target/riscv/gdbstub.c | 36 ++++++++++++++++++++++++++++++++++-- > 4 files changed, 58 insertions(+), 4 deletions(-) > >