| Message ID | 1570529884-20888-1-git-send-email-yoshihiro.shimoda.uh@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | PCI: rcar: Fix writing the MACCTLR register value | expand |
Hello! On 10/08/2019 01:18 PM, Yoshihiro Shimoda wrote: > According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register > should be written by 0. To avoid unexpected behaviors from this s/by/to/. I'd also mention that this bit is set to 1 on reset. > incorrect setting, this patch fixes it. > > Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot") > Cc: <stable@vger.kernel.org> # v4.9+ > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> [...] MBR, Sergei
Hello Sergei-san, > From: Sergei Shtylyov, Sent: Wednesday, October 9, 2019 1:13 AM > > Hello! > > On 10/08/2019 01:18 PM, Yoshihiro Shimoda wrote: > > > According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register > > should be written by 0. To avoid unexpected behaviors from this > > s/by/to/. I'd also mention that this bit is set to 1 on reset. Thank you for your review! I'll fix it. Best regards, Yoshihiro Shimoda > > incorrect setting, this patch fixes it. > > > > Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot") > > Cc: <stable@vger.kernel.org> # v4.9+ > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > [...] > > MBR, Sergei
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index f6a669a..9eb9b25 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -93,6 +93,7 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define MACCTLR_RESERVED BIT(0) #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -427,7 +428,8 @@ static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) rcar_pci_write_reg(pcie, macsr, MACSR); /* Start link speed change */ - rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); + rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE | MACCTLR_RESERVED, + SPEED_CHANGE); while (timeout--) { macsr = rcar_pci_read_reg(pcie, MACSR);
According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register should be written by 0. To avoid unexpected behaviors from this incorrect setting, this patch fixes it. Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot") Cc: <stable@vger.kernel.org> # v4.9+ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pci/controller/pcie-rcar.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)