diff mbox series

[1/4] arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices

Message ID 1569250648-33857-2-git-send-email-biju.das@bp.renesas.com (mailing list archive)
State Mainlined
Commit ce21f29032ae49a0bb2a260ab5ebf4c516c9f6e9
Delegated to: Geert Uytterhoeven
Headers show
Series Add RZ/G2N OPP/Thermal/CMT/TMU support | expand

Commit Message

Biju Das Sept. 23, 2019, 2:57 p.m. UTC 
This patch adds OPPs table for CA57{0,1} cpu devices.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Geert Uytterhoeven Oct. 9, 2019, 12:05 p.m. UTC | #1 
On Mon, Sep 23, 2019 at 4:57 PM Biju Das <biju.das@bp.renesas.com> wrote:
> This patch adds OPPs table for CA57{0,1} cpu devices.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index f42f646..398bf38 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -45,6 +45,28 @@ 
 		clock-frequency = <0>;
 	};
 
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -59,6 +81,7 @@ 
 			#cooling-cells = <2>;
 			dynamic-power-coefficient = <854>;
 			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a57_1: cpu@1 {
@@ -69,6 +92,7 @@ 
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		L2_CA57: cache-controller-0 {