| Message ID | 20191021163425.83697-1-stephan@gerhold.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm/dsi: Implement qcom, dsi-phy-regulator-ldo-mode for 28nm PHY | expand |
On Mon, Oct 21, 2019 at 06:34:25PM +0200, Stephan Gerhold wrote: > The DSI PHY regulator supports two regulator modes: LDO and DCDC. > This mode can be selected using the "qcom,dsi-phy-regulator-ldo-mode" > device tree property. > > However, at the moment only the 20nm PHY driver actually implements > that option. Add a check in the 28nm PHY driver to program the > registers correctly for LDO mode. > > Tested-by: Nikita Travkin <nikitos.tr@gmail.com> # l8150 > Signed-off-by: Stephan Gerhold <stephan@gerhold.net> > --- > This is needed to make the display work on Longcheer L8150, > which has recently gained mainline support in: > https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?id=16e8e8072108426029f0c16dff7fbe77fae3df8f > > This patch is based on code from the downstream kernel: > https://source.codeaurora.org/quic/la/kernel/msm-3.10/tree/drivers/video/msm/mdss/msm_mdss_io_8974.c?h=LA.BR.1.2.9.1-02310-8x16.0#n152 > > The LDO regulator configuration is taken from msm8916-qrd.dtsi: > https://source.codeaurora.org/quic/la/kernel/msm-3.10/tree/arch/arm/boot/dts/qcom/msm8916-qrd.dtsi?h=LA.BR.1.2.9.1-02310-8x16.0#n56 > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index b3f678f6c2aa..4579e6de4532 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -48,6 +48,25 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) > return; > } > > + if (phy->regulator_ldo_mode) { > + u32 ldo_ctrl; > + > + if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) > + ldo_ctrl = 0x05; > + else > + ldo_ctrl = 0x0d; > + > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); > + dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, ldo_ctrl); > + return; > + } nit: Since this has minimal overlap with DCDC mode, I think it would read better if you split this into 2 functions: dsi_28nm_phy_regulator_enable_dcdc() and dsi_28nm_phy_regulator_enable_ldo() So regulator_ctrl would look like: static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) { void __iomem *base = phy->reg_base; if (!enable) { dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); return; } if (phy->regulator_ldo_mode) dsi_28nm_phy_regulator_enable_ldo() else dsi_28nm_phy_regulator_enable_dcdc() } > + > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); > @@ -56,6 +75,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); > + dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); > } > > static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, > @@ -77,8 +97,6 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, > > dsi_28nm_phy_regulator_ctrl(phy, true); > > - dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); > - > dsi_28nm_dphy_set_timing(phy, timing); > > dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00); > -- > 2.23.0 >
On Mon, Oct 21, 2019 at 01:47:19PM -0400, Sean Paul wrote: > On Mon, Oct 21, 2019 at 06:34:25PM +0200, Stephan Gerhold wrote: > > The DSI PHY regulator supports two regulator modes: LDO and DCDC. > > This mode can be selected using the "qcom,dsi-phy-regulator-ldo-mode" > > device tree property. > > > > However, at the moment only the 20nm PHY driver actually implements > > that option. Add a check in the 28nm PHY driver to program the > > registers correctly for LDO mode. > > > > Tested-by: Nikita Travkin <nikitos.tr@gmail.com> # l8150 > > Signed-off-by: Stephan Gerhold <stephan@gerhold.net> > > --- > > This is needed to make the display work on Longcheer L8150, > > which has recently gained mainline support in: > > https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?id=16e8e8072108426029f0c16dff7fbe77fae3df8f > > > > This patch is based on code from the downstream kernel: > > https://source.codeaurora.org/quic/la/kernel/msm-3.10/tree/drivers/video/msm/mdss/msm_mdss_io_8974.c?h=LA.BR.1.2.9.1-02310-8x16.0#n152 > > > > The LDO regulator configuration is taken from msm8916-qrd.dtsi: > > https://source.codeaurora.org/quic/la/kernel/msm-3.10/tree/arch/arm/boot/dts/qcom/msm8916-qrd.dtsi?h=LA.BR.1.2.9.1-02310-8x16.0#n56 > > --- > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 22 ++++++++++++++++++++-- > > 1 file changed, 20 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > index b3f678f6c2aa..4579e6de4532 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > > @@ -48,6 +48,25 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) > > return; > > } > > > > + if (phy->regulator_ldo_mode) { > > + u32 ldo_ctrl; > > + > > + if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) > > + ldo_ctrl = 0x05; > > + else > > + ldo_ctrl = 0x0d; > > + > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); > > + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); > > + dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, ldo_ctrl); > > + return; > > + } > > nit: Since this has minimal overlap with DCDC mode, I think it would read better > if you split this into 2 functions: > dsi_28nm_phy_regulator_enable_dcdc() and dsi_28nm_phy_regulator_enable_ldo() > > So regulator_ctrl would look like: > > static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) > { > void __iomem *base = phy->reg_base; > > if (!enable) { > dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); > return; > } > > if (phy->regulator_ldo_mode) > dsi_28nm_phy_regulator_enable_ldo() > else > dsi_28nm_phy_regulator_enable_dcdc() > } > I implemented it similar to dsi_phy_20nm.c [1], which looks like: static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) { void __iomem *base = phy->reg_base; if (!enable) { dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0); return; } if (phy->regulator_ldo_mode) { dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d); return; } /* non LDO mode */ dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03); dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03); dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00); dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20); dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01); dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00); dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03); } I guess it looks better for the 20nm PHY driver since it writes only a single register in LDO mode rather than the full regulator configuration. I'll update my patch and send a v2. Thanks for the suggestion! [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c#n42
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index b3f678f6c2aa..4579e6de4532 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -48,6 +48,25 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) return; } + if (phy->regulator_ldo_mode) { + u32 ldo_ctrl; + + if (phy->cfg->type == MSM_DSI_PHY_28NM_LP) + ldo_ctrl = 0x05; + else + ldo_ctrl = 0x0d; + + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0x7); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x1); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x1); + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); + dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, ldo_ctrl); + return; + } + dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); @@ -56,6 +75,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); + dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); } static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, @@ -77,8 +97,6 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_28nm_phy_regulator_ctrl(phy, true); - dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); - dsi_28nm_dphy_set_timing(phy, timing); dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00);