diff mbox series

[2/5] drm/i915/display: Handle fused off HDCP

Message ID 20191019004124.371929-2-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/5] drm/i915/display: Handle fused off display correctly | expand

Commit Message

Souza, Jose Oct. 19, 2019, 12:41 a.m. UTC 
HDCP could be fused off, so not all GEN9+ platforms will support it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
 drivers/gpu/drm/i915/i915_pci.c           | 2 ++
 drivers/gpu/drm/i915/i915_reg.h           | 1 +
 drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h  | 1 +
 5 files changed, 8 insertions(+), 1 deletion(-)

Comments

Ramalingam C Oct. 23, 2019, 1:37 p.m. UTC | #1 
On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
Here HDCP stands for HDCP1.4, so please call it so.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
>  drivers/gpu/drm/i915/i915_reg.h           | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
>  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
>  5 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
>  }
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f9a3bfe68689..f2280709c8c9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_logical_ring_preemption = 1, \
>  	.display.has_csr = 1, \
>  	.has_gt_uc = 1, \
> +	.display.has_hdcp = 1, \
We dont support HDCP1.4 on chv, though hw supports it.
>  	.display.has_ipc = 1, \
>  	.ddb_size = 896
>  
> @@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.display.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
>  	.display.has_fbc = 1, \
> +	.display.has_hdcp = 1, \
Need not add for each platform, Instead add it into GEN9_FEATURES and GEN9_LP_FEATURES.
HDCP1.4 is supported on all Gen 9+ unless it is fused off.

-Ram.
>  	.display.has_psr = 1, \
>  	.has_runtime_pm = 1, \
>  	.display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e3ae6e9cbb8..eacc5ba307b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>  
>  #define SKL_DFSM				_MMIO(0x51000)
>  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 8d6492afdd6a..753c2cf2fbf4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (!enabled_mask)
>  			i915_modparams.disable_display = true;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> +			info->display.has_hdcp = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e9940f932d26..118d922261e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
>  	func(has_dsb); \
>  	func(has_fbc); \
>  	func(has_gmch); \
> +	func(has_hdcp); \
>  	func(has_hotplug); \
>  	func(has_ipc); \
>  	func(has_modular_fia); \
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Souza, Jose Oct. 23, 2019, 6:54 p.m. UTC | #2 
On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > HDCP could be fused off, so not all GEN9+ platforms will support
> > it.
> Here HDCP stands for HDCP1.4, so please call it so.

Okay, will update the commit description with the version.


> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Martin Peres <martin.peres@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> >  5 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index e69fa34528df..f1f41ca8402b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > work_struct *work)
> >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > port port)
> >  {
> >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> >  }
> >  
> >  static int
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f9a3bfe68689..f2280709c8c9 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > intel_cherryview_info = {
> >  	.has_logical_ring_preemption = 1, \
> >  	.display.has_csr = 1, \
> >  	.has_gt_uc = 1, \
> > +	.display.has_hdcp = 1, \
> We dont support HDCP1.4 on chv, though hw supports it.
> >  	.display.has_ipc = 1, \
> >  	.ddb_size = 896
> >  
> > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > intel_skylake_gt4_info = {
> >  	.display.has_ddi = 1, \
> >  	.has_fpga_dbg = 1, \
> >  	.display.has_fbc = 1, \
> > +	.display.has_hdcp = 1, \
> Need not add for each platform, Instead add it into GEN9_FEATURES and
> GEN9_LP_FEATURES.
> HDCP1.4 is supported on all Gen 9+ unless it is fused off.

It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
diff it what you commented, you can check the real output of this patch
here:

https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c


> 
> -Ram.
> >  	.display.has_psr = 1, \
> >  	.has_runtime_pm = 1, \
> >  	.display.has_csr = 1, \
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7653,6 +7653,7 @@ enum {
> >  
> >  #define SKL_DFSM				_MMIO(0x51000)
> >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 8d6492afdd6a..753c2cf2fbf4 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > drm_i915_private *dev_priv)
> >  
> >  		if (!enabled_mask)
> >  			i915_modparams.disable_display = true;
> > +
> > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > +			info->display.has_hdcp = 0;
> >  	}
> >  
> >  	/* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index e9940f932d26..118d922261e2 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> >  	func(has_dsb); \
> >  	func(has_fbc); \
> >  	func(has_gmch); \
> > +	func(has_hdcp); \
> >  	func(has_hotplug); \
> >  	func(has_ipc); \
> >  	func(has_modular_fia); \
> > -- 
> > 2.23.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ramalingam C Oct. 24, 2019, 6:57 a.m. UTC | #3 
On 2019-10-24 at 00:24:00 +0530, Souza, Jose wrote:
> On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > > HDCP could be fused off, so not all GEN9+ platforms will support
> > > it.
> > Here HDCP stands for HDCP1.4, so please call it so.
> 
> Okay, will update the commit description with the version.
> 
> 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Martin Peres <martin.peres@linux.intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > >  drivers/gpu/drm/i915/i915_pci.c           | 2 ++
> > >  drivers/gpu/drm/i915/i915_reg.h           | 1 +
> > >  drivers/gpu/drm/i915/intel_device_info.c  | 3 +++
> > >  drivers/gpu/drm/i915/intel_device_info.h  | 1 +
> > >  5 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > index e69fa34528df..f1f41ca8402b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > > work_struct *work)
> > >  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > > port port)
> > >  {
> > >  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> > > -	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > > +	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> > >  }
> > >  
> > >  static int
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index f9a3bfe68689..f2280709c8c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > > intel_cherryview_info = {
> > >  	.has_logical_ring_preemption = 1, \
> > >  	.display.has_csr = 1, \
> > >  	.has_gt_uc = 1, \
> > > +	.display.has_hdcp = 1, \
> > We dont support HDCP1.4 on chv, though hw supports it.
> > >  	.display.has_ipc = 1, \
> > >  	.ddb_size = 896
> > >  
> > > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > > intel_skylake_gt4_info = {
> > >  	.display.has_ddi = 1, \
> > >  	.has_fpga_dbg = 1, \
> > >  	.display.has_fbc = 1, \
> > > +	.display.has_hdcp = 1, \
> > Need not add for each platform, Instead add it into GEN9_FEATURES and
> > GEN9_LP_FEATURES.
> > HDCP1.4 is supported on all Gen 9+ unless it is fused off.
> 
> It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
> diff it what you commented, you can check the real output of this patch
> here:
Yes. Got it. Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> 
> https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c
> 
> 
> > 
> > -Ram.
> > >  	.display.has_psr = 1, \
> > >  	.has_runtime_pm = 1, \
> > >  	.display.has_csr = 1, \
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7653,6 +7653,7 @@ enum {
> > >  
> > >  #define SKL_DFSM				_MMIO(0x51000)
> > >  #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> > > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
> > >  #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
> > >  #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 8d6492afdd6a..753c2cf2fbf4 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > >  
> > >  		if (!enabled_mask)
> > >  			i915_modparams.disable_display = true;
> > > +
> > > +		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > > +			info->display.has_hdcp = 0;
> > >  	}
> > >  
> > >  	/* Initialize slice/subslice/EU info */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > index e9940f932d26..118d922261e2 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> > >  	func(has_dsb); \
> > >  	func(has_fbc); \
> > >  	func(has_gmch); \
> > > +	func(has_hdcp); \
> > >  	func(has_hotplug); \
> > >  	func(has_ipc); \
> > >  	func(has_modular_fia); \
> > > -- 
> > > 2.23.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e69fa34528df..f1f41ca8402b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -922,7 +922,7 @@  static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
+	return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
 }
 
 static int
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9a3bfe68689..f2280709c8c9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -612,6 +612,7 @@  static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_preemption = 1, \
 	.display.has_csr = 1, \
 	.has_gt_uc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
 	.ddb_size = 896
 
@@ -655,6 +656,7 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	.display.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.display.has_fbc = 1, \
+	.display.has_hdcp = 1, \
 	.display.has_psr = 1, \
 	.has_runtime_pm = 1, \
 	.display.has_csr = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e3ae6e9cbb8..eacc5ba307b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7653,6 +7653,7 @@  enum {
 
 #define SKL_DFSM				_MMIO(0x51000)
 #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE	(1 << 30)
+#define SKL_DFSM_DISPLAY_HDCP_DISABLE		(1 << 25)
 #define SKL_DFSM_CDCLK_LIMIT_MASK		(3 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_675		(0 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_540		(1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8d6492afdd6a..753c2cf2fbf4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -987,6 +987,9 @@  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 		if (!enabled_mask)
 			i915_modparams.disable_display = true;
+
+		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
+			info->display.has_hdcp = 0;
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e9940f932d26..118d922261e2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -138,6 +138,7 @@  enum intel_ppgtt_type {
 	func(has_dsb); \
 	func(has_fbc); \
 	func(has_gmch); \
+	func(has_hdcp); \
 	func(has_hotplug); \
 	func(has_ipc); \
 	func(has_modular_fia); \