| Message ID | 20191008161441.12721-8-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites | expand |
>-----Original Message----- >From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala >Sent: Tuesday, October 8, 2019 9:45 PM >To: intel-gfx@lists.freedesktop.org >Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color >keying is active > >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >The spec says that color keying and HDR mode are mutually exclusive. >So let's not enable HDR mode when color keying is active. Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >--- > drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++++ > drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++--- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > 3 files changed, 16 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c >b/drivers/gpu/drm/i915/display/intel_atomic_plane.c >index 98b7766eaa7a..f64204f6f37f 100644 >--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c >+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c >@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct >intel_crtc_state *old_crtc_ > new_crtc_state->active_planes &= ~BIT(plane->id); > new_crtc_state->nv12_planes &= ~BIT(plane->id); > new_crtc_state->c8_planes &= ~BIT(plane->id); >+ new_crtc_state->ckey_planes &= ~BIT(plane->id); > new_crtc_state->data_rate[plane->id] = 0; > new_plane_state->base.visible = false; > >@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct >intel_crtc_state *old_crtc_ > fb->format->format == DRM_FORMAT_C8) > new_crtc_state->c8_planes |= BIT(plane->id); > >+ if (new_plane_state->base.visible && >+ new_plane_state->ckey.flags) >+ new_crtc_state->ckey_planes |= BIT(plane->id); >+ > if (new_plane_state->base.visible || old_plane_state->base.visible) > new_crtc_state->update_planes |= BIT(plane->id); > >diff --git a/drivers/gpu/drm/i915/display/intel_display.c >b/drivers/gpu/drm/i915/display/intel_display.c >index a8124f01bdb2..c553a3417891 100644 >--- a/drivers/gpu/drm/i915/display/intel_display.c >+++ b/drivers/gpu/drm/i915/display/intel_display.c >@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct >intel_crtc_state *crtc_state) > POSTING_READ(PIPECONF(cpu_transcoder)); > } > >+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state) >+{ >+ u8 ckey_planes = crtc_state->ckey_planes; >+ u8 sdr_planes = crtc_state->active_planes & >+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR)); >+ >+ return !ckey_planes && !sdr_planes; >+} >+ > static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state >*crtc_state) > val |= PIPEMISC_YUV420_ENABLE | > PIPEMISC_YUV420_MODE_FULL_BLEND; > >- if (INTEL_GEN(dev_priv) >= 11 && >- (crtc_state->active_planes & ~(icl_hdr_plane_mask() | >- BIT(PLANE_CURSOR))) == 0) >+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state)) > val |= PIPEMISC_HDR_MODE_PRECISION; > > I915_WRITE(PIPEMISC(crtc->pipe), val); diff --git >a/drivers/gpu/drm/i915/display/intel_display_types.h >b/drivers/gpu/drm/i915/display/intel_display_types.h >index 40390d855815..4935ea41d3e1 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_types.h >+++ b/drivers/gpu/drm/i915/display/intel_display_types.h >@@ -949,6 +949,7 @@ struct intel_crtc_state { > u8 active_planes; > u8 nv12_planes; > u8 c8_planes; >+ u8 ckey_planes; > > /* bitmask of planes that will be updated during the commit */ > u8 update_planes; >-- >2.21.0 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 98b7766eaa7a..f64204f6f37f 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ new_crtc_state->active_planes &= ~BIT(plane->id); new_crtc_state->nv12_planes &= ~BIT(plane->id); new_crtc_state->c8_planes &= ~BIT(plane->id); + new_crtc_state->ckey_planes &= ~BIT(plane->id); new_crtc_state->data_rate[plane->id] = 0; new_plane_state->base.visible = false; @@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ fb->format->format == DRM_FORMAT_C8) new_crtc_state->c8_planes |= BIT(plane->id); + if (new_plane_state->base.visible && + new_plane_state->ckey.flags) + new_crtc_state->ckey_planes |= BIT(plane->id); + if (new_plane_state->base.visible || old_plane_state->base.visible) new_crtc_state->update_planes |= BIT(plane->id); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a8124f01bdb2..c553a3417891 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state) POSTING_READ(PIPECONF(cpu_transcoder)); } +static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state) +{ + u8 ckey_planes = crtc_state->ckey_planes; + u8 sdr_planes = crtc_state->active_planes & + ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR)); + + return !ckey_planes && !sdr_planes; +} + static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) val |= PIPEMISC_YUV420_ENABLE | PIPEMISC_YUV420_MODE_FULL_BLEND; - if (INTEL_GEN(dev_priv) >= 11 && - (crtc_state->active_planes & ~(icl_hdr_plane_mask() | - BIT(PLANE_CURSOR))) == 0) + if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state)) val |= PIPEMISC_HDR_MODE_PRECISION; I915_WRITE(PIPEMISC(crtc->pipe), val); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 40390d855815..4935ea41d3e1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -949,6 +949,7 @@ struct intel_crtc_state { u8 active_planes; u8 nv12_planes; u8 c8_planes; + u8 ckey_planes; /* bitmask of planes that will be updated during the commit */ u8 update_planes;