| Message ID | 3a1eda2f-bc4b-0958-d609-6376663faa9a@molgen.mpg.de (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 474435a058309cf1a253dbd77cac2ab89c75d4a6 |
| Delegated to: | Paul Burton |
| Headers | show |
| Series | mips/cavium-octeon: Fix typo *must* in comment | expand |
Hello, Paul Menzel wrote: > Date: Mon, 2 Sep 2019 11:55:06 +0200 Applied to mips-next. > commit 474435a05830 > https://git.kernel.org/mips/c/474435a05830 > > Fixes: 5b3b16880f ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.") > Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> > Signed-off-by: Paul Burton <paulburton@kernel.org> Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paulburton@kernel.org to report it. ]
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 95034bf5ca83..1f742c32a883 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -844,7 +844,7 @@ void __init prom_init(void) * BIST should always be enabled when doing a soft reset. L2 * Cache locking for instance is not cleared unless BIST is * enabled. Unfortunately due to a chip errata G-200 for - * Cn38XX and CN31XX, BIST msut be disabled on these parts. + * Cn38XX and CN31XX, BIST must be disabled on these parts. */ if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || OCTEON_IS_MODEL(OCTEON_CN31XX))
Date: Mon, 2 Sep 2019 11:55:06 +0200 Fixes: 5b3b16880f ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> --- arch/mips/cavium-octeon/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)