| Message ID | 20191105110651.217513-1-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 6b832a148717f1718f57805a9a4aa7f092582d15 |
| Headers | show |
| Series | arm64: dts: allwinner: a64: Re-add PMU node | expand |
Hi, On Tue, Nov 05, 2019 at 11:06:51AM +0000, Andre Przywara wrote: > As it was found recently, the Performance Monitoring Unit (PMU) on the > Allwinner A64 SoC was not generating (the right) interrupts. With the > SPI numbers from the manual the kernel did not receive any overflow > interrupts, so perf was not happy at all. > It turns out that the numbers were just off by 4, so the PMU interrupts > are from 148 to 151, not from 152 to 155 as the manual describes. > > This was found by playing around with U-Boot, which typically does not > use interrupts, so the GIC is fully available for experimentation: > With *every* PPI and SPI enabled, an overflowing PMU cycle counter was > found to set a bit in one of the GICD_ISPENDR registers, with careful > counting this was determined to be number 148. > > Tested with perf record and perf top on a Pine64-LTS. Also tested with > tasksetting to every core to confirm the assignment between IRQs and > cores. > > This somewhat "revert-fixes" commit ed3e9406bcbc ("arm64: dts: allwinner: > a64: Drop PMU node"). > > Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node") > Fixes: ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node") > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Applied, thanks for figuring this out! Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 70f4cce6be43..ba41c1b85887 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -142,6 +142,15 @@ clock-output-names = "ext-osc32k"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc";
As it was found recently, the Performance Monitoring Unit (PMU) on the Allwinner A64 SoC was not generating (the right) interrupts. With the SPI numbers from the manual the kernel did not receive any overflow interrupts, so perf was not happy at all. It turns out that the numbers were just off by 4, so the PMU interrupts are from 148 to 151, not from 152 to 155 as the manual describes. This was found by playing around with U-Boot, which typically does not use interrupts, so the GIC is fully available for experimentation: With *every* PPI and SPI enabled, an overflowing PMU cycle counter was found to set a bit in one of the GICD_ISPENDR registers, with careful counting this was determined to be number 148. Tested with perf record and perf top on a Pine64-LTS. Also tested with tasksetting to every core to confirm the assignment between IRQs and cores. This somewhat "revert-fixes" commit ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node"). Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node") Fixes: ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node") Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)