| Message ID | 20191107092039.32240-1-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] riscv: move sifive_l2_cache.c to drivers/soc | expand |
On Thu, Nov 07, 2019 at 10:20:39AM +0100, Christoph Hellwig wrote: > The sifive_l2_cache.c is in no way related to RISC-V architecture > memory management. It is a little stub driver working around the fact > that the EDAC maintainers prefer their drivers to be structured in a > certain way that doesn't fit the SiFive SOCs. > > Move the file to drivers/soc and add a Kconfig option for it, as well > as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > > Changes since v2: > - don't allow modular builds > - remove the empty last line in the new Makefile > > MAINTAINERS | 1 + > arch/riscv/mm/Makefile | 1 - > drivers/edac/Kconfig | 2 +- > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/sifive/Kconfig | 10 ++++++++++ > drivers/soc/sifive/Makefile | 3 +++ > .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0 > 8 files changed, 17 insertions(+), 2 deletions(-) > create mode 100644 drivers/soc/sifive/Kconfig > create mode 100644 drivers/soc/sifive/Makefile > rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%) Reviewed-by: Borislav Petkov <bp@suse.de>
diff --git a/MAINTAINERS b/MAINTAINERS index cba1095547fd..f5a8accb0df3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5972,6 +5972,7 @@ M: Yash Shah <yash.shah@sifive.com> L: linux-edac@vger.kernel.org S: Supported F: drivers/edac/sifive_edac.c +F: drivers/soc/sifive/ EDAC-SKYLAKE M: Tony Luck <tony.luck@intel.com> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 9d9a17335686..b225134c29e0 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -11,7 +11,6 @@ obj-y += extable.o obj-y += ioremap.o obj-y += cacheflush.o obj-y += context.o -obj-y += sifive_l2_cache.o ifeq ($(CONFIG_MMU),y) obj-$(CONFIG_SMP) += tlbflush.o diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 417dad635526..5c8272329a65 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=y && RISCV + depends on EDAC=y && SIFIVE_L2 help Support for error detection and correction on the SiFive SoCs. diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 833e04a7835c..1778f8c62861 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" +source "drivers/soc/sifive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 2ec355003524..8b49d782a1ab 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -20,6 +20,7 @@ obj-y += qcom/ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ +obj-$(CONFIG_SOC_SIFIVE) += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig new file mode 100644 index 000000000000..58cf8c40d08d --- /dev/null +++ b/drivers/soc/sifive/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +if SOC_SIFIVE + +config SIFIVE_L2 + bool "Sifive L2 Cache controller" + help + Support for the L2 cache controller on SiFive platforms. + +endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile new file mode 100644 index 000000000000..b5caff77938f --- /dev/null +++ b/drivers/soc/sifive/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c similarity index 100% rename from arch/riscv/mm/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_l2_cache.c
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> --- Changes since v2: - don't allow modular builds - remove the empty last line in the new Makefile MAINTAINERS | 1 + arch/riscv/mm/Makefile | 1 - drivers/edac/Kconfig | 2 +- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/sifive/Kconfig | 10 ++++++++++ drivers/soc/sifive/Makefile | 3 +++ .../riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c | 0 8 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 drivers/soc/sifive/Kconfig create mode 100644 drivers/soc/sifive/Makefile rename {arch/riscv/mm => drivers/soc/sifive}/sifive_l2_cache.c (100%)