diff mbox series

[PATCHi,v3,1/3] arm64: dts: mt8183: add dsi node

Message ID 20191028115039.96555-2-jitao.shi@mediatek.com (mailing list archive)
State New, archived
Headers show
Series add dsi pwm0 node for mt8183 | expand

Commit Message

Jitao Shi Oct. 28, 2019, 11:50 a.m. UTC 
Add dsi and mipitx nodes to the mt8183

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Matthias Brugger Nov. 10, 2019, 7:43 p.m. UTC | #1 
On 28/10/2019 12:50, Jitao Shi wrote:
> Add dsi and mipitx nodes to the mt8183
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 2857583f5d60..bb0d53be6a25 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -649,6 +649,16 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		mipi_tx0: mipi-dphy@11e50000 {
> +			compatible = "mediatek,mt8183-mipi-tx";
> +			reg = <0 0x11e50000 0 0x1000>;
> +			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
> +			clock-names = "ref_clk";
> +			#clock-cells = <0>;
> +			#phy-cells = <0>;
> +			clock-output-names = "mipi_tx0_pll";
> +		};
> +
>  		efuse: efuse@11f10000 {
>  			compatible = "mediatek,mt8183-efuse",
>  				     "mediatek,efuse";
> @@ -670,6 +680,20 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		dsi0: dsi@14014000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14014000 0 0x1000>;
> +			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
> +			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> +			mediatek,syscon-dsi = <&mmsys 0x140>;

mediatek,syscon-dsi isn't defined anywhere and not used in the driver. Please
delete.

> +			clocks = <&mmsys CLK_MM_DSI0_MM>,
> +				<&mmsys CLK_MM_DSI0_IF>,
> +				<&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +		};
> +
>  		imgsys: syscon@15020000 {
>  			compatible = "mediatek,mt8183-imgsys", "syscon";
>  			reg = <0 0x15020000 0 0x1000>;
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 2857583f5d60..bb0d53be6a25 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -649,6 +649,16 @@ 
 			#clock-cells = <1>;
 		};
 
+		mipi_tx0: mipi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
+			clock-names = "ref_clk";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+		};
+
 		efuse: efuse@11f10000 {
 			compatible = "mediatek,mt8183-efuse",
 				     "mediatek,efuse";
@@ -670,6 +680,20 @@ 
 			#clock-cells = <1>;
 		};
 
+		dsi0: dsi@14014000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+			mediatek,syscon-dsi = <&mmsys 0x140>;
+			clocks = <&mmsys CLK_MM_DSI0_MM>,
+				<&mmsys CLK_MM_DSI0_IF>,
+				<&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+		};
+
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8183-imgsys", "syscon";
 			reg = <0 0x15020000 0 0x1000>;