| Message ID | 20191119175319.16561-6-peron.clem@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for H6 PWM | expand |
Hello Clément, On Tue, Nov 19, 2019 at 06:53:16PM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip which is integrated into same > package as H6 SoC. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++------------- > 1 file changed, 64 insertions(+), 28 deletions(-) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index ce83d479ba0e..a1d8851b18f0 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranteed to be completed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + sun4i_pwm->data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, > const struct pwm_state *state, > - u32 *dty, u32 *prd, unsigned int *prsclr) > + u32 *dty, u32 *prd, unsigned int *prsclr, > + bool *bypass) > { > u64 clk_rate, div = 0; > unsigned int pval, prescaler = 0; > > clk_rate = clk_get_rate(sun4i_pwm->clk); > > + *bypass = state->enabled && > + (state->period * clk_rate >= NSEC_PER_SEC) && > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > + > + /* Skip calculation of other parameters if we bypass them */ > + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) > + return 0; > + Hmm, so if my PWM doesn't support the bypass bit *bypass might still be true on return of sun4i_pwm_calculate. It doesn't hurt because the value is only used after another check of has_direct_mod_clk_output, but still this is a bit confusing. > if (sun4i_pwm->data->has_prescaler_bypass) { > /* First, test without any prescaler when available */ > prescaler = PWM_PRESCAL_MASK; > @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > { > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > - u32 ctrl; > + u32 ctrl, period, duty, val; > int ret; > - unsigned int delay_us; > + unsigned int delay_us, prescaler; > unsigned long now; > + bool bypass; > > pwm_get_state(pwm, &cstate); > > @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > spin_lock(&sun4i_pwm->ctrl_lock); > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > - if ((cstate.period != state->period) || > - (cstate.duty_cycle != state->duty_cycle)) { > - u32 period, duty, val; > - unsigned int prescaler; > + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, > + &bypass); > + if (ret) { > + dev_err(chip->dev, "period exceeds the maximum value\n"); > + spin_unlock(&sun4i_pwm->ctrl_lock); > + if (!cstate.enabled) > + clk_disable_unprepare(sun4i_pwm->clk); > + return ret; > + } > > - ret = sun4i_pwm_calculate(sun4i_pwm, state, > - &duty, &period, &prescaler); > - if (ret) { > - dev_err(chip->dev, "period exceeds the maximum value\n"); > - spin_unlock(&sun4i_pwm->ctrl_lock); > - if (!cstate.enabled) > - clk_disable_unprepare(sun4i_pwm->clk); > - return ret; This would be a bit easier to review if this commit was split into two patches. One that drops the check for cstate.period != state->period etc (which otherwise is nearly empty when ignoring whitespace changes), and a second that then adds bypass support. > + if (sun4i_pwm->data->has_direct_mod_clk_output) { > + if (bypass) { > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); > + /* We can skip apply of other parameters */ > + goto bypass_mode; I would prefer to use goto only for error handling. Not sure if there is a nice way to do that. > + } else { > + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); > } > + } Best regards Uwe
Hi Uwe, On Thu, 21 Nov 2019 at 08:36, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > Hello Clément, > > On Tue, Nov 19, 2019 at 06:53:16PM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > PWM core has an option to bypass whole logic and output unchanged source > > clock as PWM output. This is achieved by enabling bypass bit. > > > > Note that when bypass is enabled, no other setting has any meaning, not > > even enable bit. > > > > This mode of operation is needed to achieve high enough frequency to > > serve as clock source for AC200 chip which is integrated into same > > package as H6 SoC. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++------------- > > 1 file changed, 64 insertions(+), 28 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index ce83d479ba0e..a1d8851b18f0 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -3,6 +3,10 @@ > > * Driver for Allwinner sun4i Pulse Width Modulation Controller > > * > > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > > + * > > + * Limitations: > > + * - When outputing the source clock directly, the PWM logic will be bypassed > > + * and the currently running period is not guaranteed to be completed > > */ > > > > #include <linux/bitops.h> > > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_direct_mod_clk_output; > > unsigned int npwm; > > }; > > > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > + /* > > + * PWM chapter in H6 manual has a diagram which explains that if bypass > > + * bit is set, no other setting has any meaning. Even more, experiment > > + * proved that also enable bit is ignored in this case. > > + */ > > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > > + sun4i_pwm->data->has_direct_mod_clk_output) { > > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); > > + state->polarity = PWM_POLARITY_NORMAL; > > + state->enabled = true; > > + return; > > + } > > + > > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > > sun4i_pwm->data->has_prescaler_bypass) > > prescaler = 1; > > @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > > > static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, > > const struct pwm_state *state, > > - u32 *dty, u32 *prd, unsigned int *prsclr) > > + u32 *dty, u32 *prd, unsigned int *prsclr, > > + bool *bypass) > > { > > u64 clk_rate, div = 0; > > unsigned int pval, prescaler = 0; > > > > clk_rate = clk_get_rate(sun4i_pwm->clk); > > > > + *bypass = state->enabled && > > + (state->period * clk_rate >= NSEC_PER_SEC) && > > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > > + > > + /* Skip calculation of other parameters if we bypass them */ > > + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) > > + return 0; > > + > > Hmm, so if my PWM doesn't support the bypass bit *bypass might still be > true on return of sun4i_pwm_calculate. It doesn't hurt because the value > is only used after another check of has_direct_mod_clk_output, but still > this is a bit confusing. Ok will change this > > > if (sun4i_pwm->data->has_prescaler_bypass) { > > /* First, test without any prescaler when available */ > > prescaler = PWM_PRESCAL_MASK; > > @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > { > > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > > struct pwm_state cstate; > > - u32 ctrl; > > + u32 ctrl, period, duty, val; > > int ret; > > - unsigned int delay_us; > > + unsigned int delay_us, prescaler; > > unsigned long now; > > + bool bypass; > > > > pwm_get_state(pwm, &cstate); > > > > @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > spin_lock(&sun4i_pwm->ctrl_lock); > > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > - if ((cstate.period != state->period) || > > - (cstate.duty_cycle != state->duty_cycle)) { > > - u32 period, duty, val; > > - unsigned int prescaler;n write the register and return But > > + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, > > + &bypass); > > + if (ret) { > > + dev_err(chip->dev, "period exceeds the maximum value\n"); > > + spin_unlock(&sun4i_pwm->ctrl_lock); > > + if (!cstate.enabled) > > + clk_disable_unprepare(sun4i_pwm->clk); > > + return ret; > > + } > > > > - ret = sun4i_pwm_calculate(sun4i_pwm, state, > > - &duty, &period, &prescaler); > > - if (ret) { > > - dev_err(chip->dev, "period exceeds the maximum value\n"); > > - spin_unlock(&sun4i_pwm->ctrl_lock); > > - if (!cstate.enabled) > > - clk_disable_unprepare(sun4i_pwm->clk); > > - return ret; > > This would be a bit easier to review if this commit was split into two > patches. One that drops the check for cstate.period != state->period etc > (which otherwise is nearly empty when ignoring whitespace changes), and > a second that then adds bypass support. Ok > > > > + if (sun4i_pwm->data->has_direct_mod_clk_output) { > > + if (bypass) { > > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); > > + /* We can skip apply of other parameters */ > > + goto bypass_mode; > > I would prefer to use goto only for error handling. Not sure if there is > a nice way to do that. As the PWM is necessarily enabled we can write the register and return but not sure it's more proper. sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); return 0; Regards, Clément > > > + } else { > > + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); > > } > > + } > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ |
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index ce83d479ba0e..a1d8851b18f0 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include <linux/bitops.h> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, const struct pwm_state *state, - u32 *dty, u32 *prd, unsigned int *prsclr) + u32 *dty, u32 *prd, unsigned int *prsclr, + bool *bypass) { u64 clk_rate, div = 0; unsigned int pval, prescaler = 0; clk_rate = clk_get_rate(sun4i_pwm->clk); + *bypass = state->enabled && + (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + + /* Skip calculation of other parameters if we bypass them */ + if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output) + return 0; + if (sun4i_pwm->data->has_prescaler_bypass) { /* First, test without any prescaler when available */ prescaler = PWM_PRESCAL_MASK; @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, period, duty, val; int ret; - unsigned int delay_us; + unsigned int delay_us, prescaler; unsigned long now; + bool bypass; pwm_get_state(pwm, &cstate); @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - if ((cstate.period != state->period) || - (cstate.duty_cycle != state->duty_cycle)) { - u32 period, duty, val; - unsigned int prescaler; + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, + &bypass); + if (ret) { + dev_err(chip->dev, "period exceeds the maximum value\n"); + spin_unlock(&sun4i_pwm->ctrl_lock); + if (!cstate.enabled) + clk_disable_unprepare(sun4i_pwm->clk); + return ret; + } - ret = sun4i_pwm_calculate(sun4i_pwm, state, - &duty, &period, &prescaler); - if (ret) { - dev_err(chip->dev, "period exceeds the maximum value\n"); - spin_unlock(&sun4i_pwm->ctrl_lock); - if (!cstate.enabled) - clk_disable_unprepare(sun4i_pwm->clk); - return ret; + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) { + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + /* We can skip apply of other parameters */ + goto bypass_mode; + } else { + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); } + } - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { - /* Prescaler changed, the clock has to be gated */ - ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - - ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); - ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } + if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { + /* Prescaler changed, the clock has to be gated */ + ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - val = (duty & PWM_DTY_MASK) | PWM_PRD(period); - sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); - sun4i_pwm->next_period[pwm->hwpwm] = jiffies + - usecs_to_jiffies(cstate.period / 1000 + 1); - sun4i_pwm->needs_delay[pwm->hwpwm] = true; + ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); + ctrl |= BIT_CH(prescaler, pwm->hwpwm); } + val = (duty & PWM_DTY_MASK) | PWM_PRD(period); + sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); + sun4i_pwm->next_period[pwm->hwpwm] = jiffies + + usecs_to_jiffies(cstate.period / 1000 + 1); + sun4i_pwm->needs_delay[pwm->hwpwm] = true; + if (state->polarity != PWM_POLARITY_NORMAL) ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); else ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -264,6 +299,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock);