| Message ID | c73e2cee4f818654f264b0b7b5458bfaa0ac6a7a.1574595627.git.hns@goldelico.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Paul Burton |
| Headers | show |
| Series | ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) | expand |
Hi Nikolaus, Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > and add interrupt and clocks. > > Tested to build for CI20 board and load a (non-working) driver. > > Suggested-by: Paul Boddie <paul@boddie.org.uk> > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi > b/arch/mips/boot/dts/ingenic/jz4780.dtsi > index c54bd7cfec55..21ea5f4a405b 100644 > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi > @@ -46,6 +46,17 @@ > #clock-cells = <1>; > }; > > + gpu: gpu@13040000 { We try to keep the nodes ordered by address, could you move this node where it belongs? Thanks, -Paul > + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", > "img,sgx540", "img,sgx5"; > + reg = <0x13040000 0x4000>; > + > + clocks = <&cgu JZ4780_CLK_GPU>; > + clock-names = "gpu"; > + > + interrupt-parent = <&intc>; > + interrupts = <63>; > + }; > + > tcu: timer@10002000 { > compatible = "ingenic,jz4780-tcu", > "ingenic,jz4770-tcu", > -- > 2.23.0 >
* Paul Cercueil <paul@crapouillou.net> [191124 12:58]: > Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <hns@goldelico.com> a > écrit : > > and add interrupt and clocks. ... > > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi > > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi > > @@ -46,6 +46,17 @@ > > #clock-cells = <1>; > > }; > > > > + gpu: gpu@13040000 { > > We try to keep the nodes ordered by address, could you move this node where > it belongs? ... > > + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", > > "img,sgx540", "img,sgx5"; > > + reg = <0x13040000 0x4000>; > > + > > + clocks = <&cgu JZ4780_CLK_GPU>; > > + clock-names = "gpu"; Just checking.. Is there something else to configure here potentially in addition to the clocks? That is, do we need to do some interconnect specific configuration etc in addition to the clocks to have runtime PM work for enabling and disabling sgx on jz4780? Regards, Tony
Hi Paul, Tony, > Am 24.11.2019 um 18:48 schrieb Tony Lindgren <tony@atomide.com>: > > * Paul Cercueil <paul@crapouillou.net> [191124 12:58]: >> Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <hns@goldelico.com> a >> écrit : >>> and add interrupt and clocks. > ... >>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> @@ -46,6 +46,17 @@ >>> #clock-cells = <1>; >>> }; >>> >>> + gpu: gpu@13040000 { >> >> We try to keep the nodes ordered by address, could you move this node where >> it belongs? > ... Yes, I have noted. > >>> + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", >>> "img,sgx540", "img,sgx5"; >>> + reg = <0x13040000 0x4000>; >>> + >>> + clocks = <&cgu JZ4780_CLK_GPU>; >>> + clock-names = "gpu"; > > Just checking.. Is there something else to configure here > potentially in addition to the clocks? It doesn't look so. Unfortuantely there isn't much information except a v3.18 kernel supported by the vendor and that one also just has a gpu node with clock control. > That is, do we need to do some interconnect specific > configuration etc in addition to the clocks to have > runtime PM work for enabling and disabling sgx on > jz4780? I think we have to leave that open for further study. BR, Nikolaus
* H. Nikolaus Schaller <hns@goldelico.com> [191124 18:00]: > Hi Paul, Tony, > > > Am 24.11.2019 um 18:48 schrieb Tony Lindgren <tony@atomide.com>: > > > > * Paul Cercueil <paul@crapouillou.net> [191124 12:58]: > >> Le dim., nov. 24, 2019 at 12:40, H. Nikolaus Schaller <hns@goldelico.com> a > >> écrit : > >>> and add interrupt and clocks. > > ... > >>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi > >>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi > >>> @@ -46,6 +46,17 @@ > >>> #clock-cells = <1>; > >>> }; > >>> > >>> + gpu: gpu@13040000 { > >> > >> We try to keep the nodes ordered by address, could you move this node where > >> it belongs? > > ... > > Yes, I have noted. > > > > >>> + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", > >>> "img,sgx540", "img,sgx5"; > >>> + reg = <0x13040000 0x4000>; > >>> + > >>> + clocks = <&cgu JZ4780_CLK_GPU>; > >>> + clock-names = "gpu"; > > > > Just checking.. Is there something else to configure here > > potentially in addition to the clocks? > > It doesn't look so. Unfortuantely there isn't much information > except a v3.18 kernel supported by the vendor and that one also > just has a gpu node with clock control. > > > That is, do we need to do some interconnect specific > > configuration etc in addition to the clocks to have > > runtime PM work for enabling and disabling sgx on > > jz4780? > > I think we have to leave that open for further study. OK for now, let's assume we just need to call clk_enable/disable from the PM runtime functions if a clock exists. Regards, Tony
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index c54bd7cfec55..21ea5f4a405b 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -46,6 +46,17 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120", "img,sgx540", "img,sgx5"; + reg = <0x13040000 0x4000>; + + clocks = <&cgu JZ4780_CLK_GPU>; + clock-names = "gpu"; + + interrupt-parent = <&intc>; + interrupts = <63>; + }; + tcu: timer@10002000 { compatible = "ingenic,jz4780-tcu", "ingenic,jz4770-tcu",
and add interrupt and clocks. Tested to build for CI20 board and load a (non-working) driver. Suggested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> --- arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)