| Message ID | 1574664121-13451-1-git-send-email-radhey.shyam.pandey@xilinx.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all | expand |
On 25-11-19, 12:12, Radhey Shyam Pandey wrote: > Reset DMA channel after stop to ensure that pending transfers and FIFOs > in the datapath are flushed or completed. It fixes intermittent data > verification failure reported by xilinx dma test client. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index a9c5d5c..6f1539c 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan) > u32 reg; > int err; > > - if (chan->cyclic) > - xilinx_dma_chan_reset(chan); So reset is required for non cyclic cases as well now? > - > - err = chan->stop_transfer(chan); > - if (err) { > - dev_err(chan->dev, "Cannot stop channel %p: %x\n", > - chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); > - chan->err = true; > + if (!chan->cyclic) { > + err = chan->stop_transfer(chan); no stop for cyclic now..? > + if (err) { > + dev_err(chan->dev, "Cannot stop channel %p: %x\n", > + chan, dma_ctrl_read(chan, > + XILINX_DMA_REG_DMASR)); > + chan->err = true; > + } > } > > + xilinx_dma_chan_reset(chan); > /* Remove and free all of the descriptors in the lists */ > xilinx_dma_free_descriptors(chan); > chan->idle = true; > -- > 2.7.4
> -----Original Message----- > From: Vinod Koul <vkoul@kernel.org> > Sent: Tuesday, December 10, 2019 11:31 AM > To: Radhey Shyam Pandey <radheys@xilinx.com> > Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; > nick.graumann@gmail.com; andrea.merello@gmail.com; Appana Durga > Kedareswara Rao <appanad@xilinx.com>; mcgrof@kernel.org; > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; git > <git@xilinx.com> > Subject: Re: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in > dma_terminate_all > > On 25-11-19, 12:12, Radhey Shyam Pandey wrote: > > Reset DMA channel after stop to ensure that pending transfers and > > FIFOs in the datapath are flushed or completed. It fixes intermittent > > data verification failure reported by xilinx dma test client. > > > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > --- > > drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > > b/drivers/dma/xilinx/xilinx_dma.c index a9c5d5c..6f1539c 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct > dma_chan *dchan) > > u32 reg; > > int err; > > > > - if (chan->cyclic) > > - xilinx_dma_chan_reset(chan); > > So reset is required for non cyclic cases as well now? Yes. In absence of reset in non-cyclic case, when dmatest client driver is stressed and loaded/unloaded multiple times we see dma data comparison failures. Possibly IP is prefetching/holding the previous state and reset ensures a clean state on each iteration. > > > - > > - err = chan->stop_transfer(chan); > > - if (err) { > > - dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > - chan, dma_ctrl_read(chan, > XILINX_DMA_REG_DMASR)); > > - chan->err = true; > > + if (!chan->cyclic) { > > + err = chan->stop_transfer(chan); > > no stop for cyclic now..? After reset stop is not needed, so for the cyclic mode we only do reset. > > > + if (err) { > > + dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > + chan, dma_ctrl_read(chan, > > + XILINX_DMA_REG_DMASR)); > > + chan->err = true; > > + } > > } > > > > + xilinx_dma_chan_reset(chan); > > /* Remove and free all of the descriptors in the lists */ > > xilinx_dma_free_descriptors(chan); > > chan->idle = true; > > -- > > 2.7.4 > > -- > ~Vinod
On 11-12-19, 14:46, Radhey Shyam Pandey wrote: > > -----Original Message----- > > From: Vinod Koul <vkoul@kernel.org> > > Sent: Tuesday, December 10, 2019 11:31 AM > > To: Radhey Shyam Pandey <radheys@xilinx.com> > > Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; > > nick.graumann@gmail.com; andrea.merello@gmail.com; Appana Durga > > Kedareswara Rao <appanad@xilinx.com>; mcgrof@kernel.org; > > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; git > > <git@xilinx.com> > > Subject: Re: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in > > dma_terminate_all > > > > On 25-11-19, 12:12, Radhey Shyam Pandey wrote: > > > Reset DMA channel after stop to ensure that pending transfers and > > > FIFOs in the datapath are flushed or completed. It fixes intermittent > > > data verification failure reported by xilinx dma test client. > > > > > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > > --- > > > drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- > > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > > > b/drivers/dma/xilinx/xilinx_dma.c index a9c5d5c..6f1539c 100644 > > > --- a/drivers/dma/xilinx/xilinx_dma.c > > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > > @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct > > dma_chan *dchan) > > > u32 reg; > > > int err; > > > > > > - if (chan->cyclic) > > > - xilinx_dma_chan_reset(chan); > > > > So reset is required for non cyclic cases as well now? > > Yes. In absence of reset in non-cyclic case, when dmatest client > driver is stressed and loaded/unloaded multiple times we see dma > data comparison failures. Possibly IP is prefetching/holding the > previous state and reset ensures a clean state on each iteration. > > > > > - > > > - err = chan->stop_transfer(chan); > > > - if (err) { > > > - dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > > - chan, dma_ctrl_read(chan, > > XILINX_DMA_REG_DMASR)); > > > - chan->err = true; > > > + if (!chan->cyclic) { > > > + err = chan->stop_transfer(chan); > > > > no stop for cyclic now..? > After reset stop is not needed, so for the cyclic mode we only do reset. Okay makes sense, can you please add these as comments, down the line these will be very useful for you & others to debug!
> -----Original Message----- > From: Vinod Koul <vkoul@kernel.org> > Sent: Wednesday, December 18, 2019 11:35 AM > To: Radhey Shyam Pandey <radheys@xilinx.com> > Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; > nick.graumann@gmail.com; andrea.merello@gmail.com; Appana Durga > Kedareswara Rao <appanad@xilinx.com>; mcgrof@kernel.org; > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; git > <git@xilinx.com> > Subject: Re: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in > dma_terminate_all > > On 11-12-19, 14:46, Radhey Shyam Pandey wrote: > > > -----Original Message----- > > > From: Vinod Koul <vkoul@kernel.org> > > > Sent: Tuesday, December 10, 2019 11:31 AM > > > To: Radhey Shyam Pandey <radheys@xilinx.com> > > > Cc: dan.j.williams@intel.com; Michal Simek <michals@xilinx.com>; > > > nick.graumann@gmail.com; andrea.merello@gmail.com; Appana Durga > > > Kedareswara Rao <appanad@xilinx.com>; mcgrof@kernel.org; > > > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; git > > > <git@xilinx.com> > > > Subject: Re: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in > > > dma_terminate_all > > > > > > On 25-11-19, 12:12, Radhey Shyam Pandey wrote: > > > > Reset DMA channel after stop to ensure that pending transfers and > > > > FIFOs in the datapath are flushed or completed. It fixes intermittent > > > > data verification failure reported by xilinx dma test client. > > > > > > > > Signed-off-by: Radhey Shyam Pandey > <radhey.shyam.pandey@xilinx.com> > > > > --- > > > > drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- > > > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > > > > b/drivers/dma/xilinx/xilinx_dma.c index a9c5d5c..6f1539c 100644 > > > > --- a/drivers/dma/xilinx/xilinx_dma.c > > > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > > > @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct > > > dma_chan *dchan) > > > > u32 reg; > > > > int err; > > > > > > > > - if (chan->cyclic) > > > > - xilinx_dma_chan_reset(chan); > > > > > > So reset is required for non cyclic cases as well now? > > > > Yes. In absence of reset in non-cyclic case, when dmatest client > > driver is stressed and loaded/unloaded multiple times we see dma > > data comparison failures. Possibly IP is prefetching/holding the > > previous state and reset ensures a clean state on each iteration. > > > > > > > - > > > > - err = chan->stop_transfer(chan); > > > > - if (err) { > > > > - dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > > > - chan, dma_ctrl_read(chan, > > > XILINX_DMA_REG_DMASR)); > > > > - chan->err = true; > > > > + if (!chan->cyclic) { > > > > + err = chan->stop_transfer(chan); > > > > > > no stop for cyclic now..? > > After reset stop is not needed, so for the cyclic mode we only do reset. > > Okay makes sense, can you please add these as comments, down the line > these will be very useful for you & others to debug! Thanks for the review. I agree, will include the comments in v2. > > -- > ~Vinod
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index a9c5d5c..6f1539c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan) u32 reg; int err; - if (chan->cyclic) - xilinx_dma_chan_reset(chan); - - err = chan->stop_transfer(chan); - if (err) { - dev_err(chan->dev, "Cannot stop channel %p: %x\n", - chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); - chan->err = true; + if (!chan->cyclic) { + err = chan->stop_transfer(chan); + if (err) { + dev_err(chan->dev, "Cannot stop channel %p: %x\n", + chan, dma_ctrl_read(chan, + XILINX_DMA_REG_DMASR)); + chan->err = true; + } } + xilinx_dma_chan_reset(chan); /* Remove and free all of the descriptors in the lists */ xilinx_dma_free_descriptors(chan); chan->idle = true;
Reset DMA channel after stop to ensure that pending transfers and FIFOs in the datapath are flushed or completed. It fixes intermittent data verification failure reported by xilinx dma test client. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> --- drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)