| Message ID | 583761dfb63e63f7b5d5ae5fccee91c84d57a548.1575907078.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dsi: enable DSC | expand |
On Mon, 09 Dec 2019, Jani Nikula <jani.nikula@intel.com> wrote: > Add basic hardware state readout for DSC, and check the most relevant > details in the state checker. > > As a side effect, this should also get the power domains for the enabled > DSC on takeover, and subsequently disable DSC if it's not needed. This was hasty... Need to check for source DSC support and DSC power domain power before readout. Duh. BR, Jani. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > drivers/gpu/drm/i915/display/intel_display.c | 4 +++ > drivers/gpu/drm/i915/display/intel_vdsc.c | 36 ++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++ > 4 files changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 3cacb1e279c1..98964d127cd1 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4291,6 +4291,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) > return; > > + intel_dsc_get_config(encoder, pipe_config); > + > temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); > if (temp & TRANS_DDI_PHSYNC) > flags |= DRM_MODE_FLAG_PHSYNC; > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 3190aa27ffdc..4fd34d2cba4f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -13316,6 +13316,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(sync_mode_slaves_mask); > PIPE_CONF_CHECK_I(master_transcoder); > > + PIPE_CONF_CHECK_I(dsc.compression_enable); > + PIPE_CONF_CHECK_I(dsc.dsc_split); > + PIPE_CONF_CHECK_I(dsc.compressed_bpp); > + > #undef PIPE_CONF_CHECK_X > #undef PIPE_CONF_CHECK_I > #undef PIPE_CONF_CHECK_BOOL > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 7bd727129a8f..4c1b1c5c55ff 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -845,6 +845,42 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > } > } > > +void intel_dsc_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + enum pipe pipe = crtc->pipe; > + u32 dss_ctl1, dss_ctl2, val; > + > + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > + dss_ctl1 = I915_READ(DSS_CTL1); > + dss_ctl2 = I915_READ(DSS_CTL2); > + } else { > + dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe)); > + dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe)); > + } > + > + crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; > + if (!crtc_state->dsc.compression_enable) > + return; > + > + crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && > + (dss_ctl1 & JOINER_ENABLE); > + > + /* FIXME: add more state readout as needed */ > + > + /* PPS1 */ > + if (cpu_transcoder == TRANSCODER_EDP) > + val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); > + else > + val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); > + vdsc_cfg->bits_per_pixel = val; > + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; > +} > + > static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h > index 4ed2256750c3..541c28a9e158 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h > @@ -14,6 +14,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, > void intel_dsc_disable(const struct intel_crtc_state *crtc_state); > int intel_dsc_compute_params(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config); > +void intel_dsc_get_config(struct intel_encoder *encoder, > + struct intel_crtc_state *crtc_state); > enum intel_display_power_domain > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3cacb1e279c1..98964d127cd1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4291,6 +4291,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) return; + intel_dsc_get_config(encoder, pipe_config); + temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (temp & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3190aa27ffdc..4fd34d2cba4f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13316,6 +13316,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(sync_mode_slaves_mask); PIPE_CONF_CHECK_I(master_transcoder); + PIPE_CONF_CHECK_I(dsc.compression_enable); + PIPE_CONF_CHECK_I(dsc.dsc_split); + PIPE_CONF_CHECK_I(dsc.compressed_bpp); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 7bd727129a8f..4c1b1c5c55ff 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -845,6 +845,42 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, } } +void intel_dsc_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum pipe pipe = crtc->pipe; + u32 dss_ctl1, dss_ctl2, val; + + if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { + dss_ctl1 = I915_READ(DSS_CTL1); + dss_ctl2 = I915_READ(DSS_CTL2); + } else { + dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe)); + dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe)); + } + + crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; + if (!crtc_state->dsc.compression_enable) + return; + + crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && + (dss_ctl1 & JOINER_ENABLE); + + /* FIXME: add more state readout as needed */ + + /* PPS1 */ + if (cpu_transcoder == TRANSCODER_EDP) + val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); + else + val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); + vdsc_cfg->bits_per_pixel = val; + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; +} + static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 4ed2256750c3..541c28a9e158 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -14,6 +14,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, void intel_dsc_disable(const struct intel_crtc_state *crtc_state); int intel_dsc_compute_params(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); +void intel_dsc_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); enum intel_display_power_domain intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
Add basic hardware state readout for DSC, and check the most relevant details in the state checker. As a side effect, this should also get the power domains for the enabled DSC on takeover, and subsequently disable DSC if it's not needed. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_display.c | 4 +++ drivers/gpu/drm/i915/display/intel_vdsc.c | 36 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++ 4 files changed, 44 insertions(+)