diff mbox series

[02/10] ppc/pnv: Introduce a "system-memory" property

Message ID 20191219073001.26790-3-clg@kaod.org (mailing list archive)
State New, archived
Headers show
Series ppc/pnv: remove the use of qdev_get_machine() and get_system_memory() | expand

Commit Message

Cédric Le Goater Dec. 19, 2019, 7:29 a.m. UTC 
and use a link to pass the system memory to the device models that
require it to map/unmap BARs. This replace the use of get_system_memory()

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/pnv.h      |  2 ++
 include/hw/ppc/pnv_psi.h  |  1 +
 include/hw/ppc/pnv_xive.h |  2 ++
 hw/intc/pnv_xive.c        |  5 ++++-
 hw/ppc/pnv.c              | 31 ++++++++++++++++++++++++-------
 hw/ppc/pnv_psi.c          | 13 ++++++++++---
 6 files changed, 43 insertions(+), 11 deletions(-)

Comments

Greg Kurz Dec. 19, 2019, 4:01 p.m. UTC | #1 
On Thu, 19 Dec 2019 08:29:53 +0100
Cédric Le Goater <clg@kaod.org> wrote:

> and use a link to pass the system memory to the device models that
> require it to map/unmap BARs. This replace the use of get_system_memory()
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---

Globally good. A few remarks, see below.

>  include/hw/ppc/pnv.h      |  2 ++
>  include/hw/ppc/pnv_psi.h  |  1 +
>  include/hw/ppc/pnv_xive.h |  2 ++
>  hw/intc/pnv_xive.c        |  5 ++++-
>  hw/ppc/pnv.c              | 31 ++++++++++++++++++++++++-------
>  hw/ppc/pnv_psi.c          | 13 ++++++++++---
>  6 files changed, 43 insertions(+), 11 deletions(-)
> 
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index f78fd0dd967c..f31180618672 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -56,6 +56,8 @@ typedef struct PnvChip {
>      AddressSpace xscom_as;
>  
>      gchar        *dt_isa_nodename;
> +
> +    MemoryRegion *system_memory;
>  } PnvChip;
>  
>  #define TYPE_PNV8_CHIP "pnv8-chip"
> diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
> index f0f5b5519767..f85babaff0be 100644
> --- a/include/hw/ppc/pnv_psi.h
> +++ b/include/hw/ppc/pnv_psi.h
> @@ -35,6 +35,7 @@ typedef struct PnvPsi {
>  
>      MemoryRegion regs_mr;
>      uint64_t bar;
> +    MemoryRegion *system_memory;
>  
>      /* FSP region not supported */
>      /* MemoryRegion fsp_mr; */
> diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
> index f4c7caad40ee..4d641db691c8 100644
> --- a/include/hw/ppc/pnv_xive.h
> +++ b/include/hw/ppc/pnv_xive.h
> @@ -30,6 +30,8 @@ typedef struct PnvXive {
>      /* Owning chip */
>      struct PnvChip *chip;
>  
> +    MemoryRegion *system_memory;
> +
>      /* XSCOM addresses giving access to the controller registers */
>      MemoryRegion  xscom_regs;
>  
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index a0a69b98a713..66970a60733b 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -853,7 +853,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
>                                    uint64_t val, unsigned size)
>  {
>      PnvXive *xive = PNV_XIVE(opaque);
> -    MemoryRegion *sysmem = get_system_memory();
> +    MemoryRegion *sysmem = xive->system_memory;
>      uint32_t reg = offset >> 3;
>      bool is_chip0 = xive->chip->chip_id == 0;
>  
> @@ -1821,6 +1821,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
>      Error *local_err = NULL;
>  
>      assert(xive->chip);
> +    assert(xive->system_memory);
>  
>      /*
>       * The XiveSource and XiveENDSource objects are realized with the
> @@ -1937,6 +1938,8 @@ static Property pnv_xive_properties[] = {
>      DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
>      /* The PnvChip id identifies the XIVE interrupt controller. */
>      DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *),
> +    DEFINE_PROP_LINK("system-memory", PnvXive, system_memory,
> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 855254f28263..2f611bfdda46 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -674,6 +674,7 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
>  
>  static void pnv_init(MachineState *machine)
>  {
> +    MemoryRegion *sysmem = get_system_memory();
>      PnvMachineState *pnv = PNV_MACHINE(machine);
>      MachineClass *mc = MACHINE_GET_CLASS(machine);
>      MemoryRegion *ram;
> @@ -692,7 +693,7 @@ static void pnv_init(MachineState *machine)
>      ram = g_new(MemoryRegion, 1);
>      memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
>                                           machine->ram_size);
> -    memory_region_add_subregion(get_system_memory(), 0, ram);
> +    memory_region_add_subregion(sysmem, 0, ram);
>  
>      /*
>       * Create our simple PNOR device
> @@ -790,6 +791,12 @@ static void pnv_init(MachineState *machine)
>                                  &error_fatal);
>          object_property_set_int(chip, machine->smp.cores,
>                                  "nr-cores", &error_fatal);
> +        /*
> +         * TODO: Only the MMIO range should be of interest for the
> +         * controllers
> +         */
> +        object_property_set_link(chip, OBJECT(sysmem), "system-memory",
> +                                 &error_abort);

Like it is done with PnvXive, it would be good to pair this with an
assert(chip->system_memory) in pnv_chip_realize().

>          object_property_set_bool(chip, true, "realized", &error_fatal);
>      }
>      g_free(chip_typename);
> @@ -1060,6 +1067,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>      /* Processor Service Interface (PSI) Host Bridge */
>      object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
>                              "bar", &error_fatal);
> +    object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip->system_memory),
> +                             "system-memory", &error_abort);
>      object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
>      if (local_err) {
>          error_propagate(errp, local_err);
> @@ -1100,7 +1109,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>      pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
>  
>      /* OCC SRAM model */
> -    memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV_OCC_SENSOR_BASE(chip),
>                                  &chip8->occ.sram_regs);
>  
>      /* HOMER */
> @@ -1116,7 +1125,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>      pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
>  
>      /* Homer mmio region */
> -    memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV_HOMER_BASE(chip),
>                                  &chip8->homer.regs);
>  }
>  
> @@ -1280,6 +1289,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>                              "tm-bar", &error_fatal);
>      object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
>                               &error_abort);
> +    object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip->system_memory),
> +                             "system-memory", &error_abort);
>      object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
>                               &local_err);
>      if (local_err) {
> @@ -1292,6 +1303,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>      /* Processor Service Interface (PSI) Host Bridge */
>      object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
>                              "bar", &error_fatal);
> +    object_property_set_link(OBJECT(&chip9->psi), OBJECT(chip->system_memory),
> +                             "system-memory", &error_abort);
>      object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
>      if (local_err) {
>          error_propagate(errp, local_err);
> @@ -1308,7 +1321,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>          error_propagate(errp, local_err);
>          return;
>      }
> -    memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV9_LPCM_BASE(chip),
>                                  &chip9->lpc.xscom_regs);
>  
>      chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
> @@ -1325,7 +1338,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>      pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
>  
>      /* OCC SRAM model */
> -    memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV9_OCC_SENSOR_BASE(chip),
>                                  &chip9->occ.sram_regs);
>  
>      /* HOMER */
> @@ -1341,7 +1354,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>      pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
>  
>      /* Homer mmio region */
> -    memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV9_HOMER_BASE(chip),
>                                  &chip9->homer.regs);
>  }
>  
> @@ -1408,6 +1421,8 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
>      /* Processor Service Interface (PSI) Host Bridge */
>      object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
>                              "bar", &error_fatal);
> +    object_property_set_link(OBJECT(&chip10->psi), OBJECT(chip->system_memory),
> +                             "system-memory", &error_abort);
>      object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
>                               &local_err);
>      if (local_err) {
> @@ -1426,7 +1441,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
>          error_propagate(errp, local_err);
>          return;
>      }
> -    memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
> +    memory_region_add_subregion(chip->system_memory, PNV10_LPCM_BASE(chip),
>                                  &chip10->lpc.xscom_regs);
>  
>      chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
> @@ -1570,6 +1585,8 @@ static Property pnv_chip_properties[] = {
>      DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
>      DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
>      DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
> +    DEFINE_PROP_LINK("system-memory", PnvChip, system_memory,
> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 75e20d9da08b..28d34e5c193a 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -126,7 +126,7 @@
>  static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
>  {
>      PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
> -    MemoryRegion *sysmem = get_system_memory();
> +    MemoryRegion *sysmem = psi->system_memory;
>      uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
>  
>      psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
> @@ -489,6 +489,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
>      Error *err = NULL;
>      unsigned int i;
>  
> +    assert(psi->system_memory);
> +

This should theoretically sit in a realize function of the base
PnvPsi class. It doesn't exist but looking at the other duplicate
code in pnv_psi_power8_realize() and pnv_psi_power9_realize(),
eg. the reset handler, it seems it could be beneficial to
introduce one.

But this is far beyond the scope of this patch, so I guess
it is okay to keep the duplicate assert() for now.

>      obj = object_property_get_link(OBJECT(dev), "xics", &err);
>      if (!obj) {
>          error_setg(errp, "%s: required link 'xics' not found: %s",
> @@ -562,6 +564,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
>  static Property pnv_psi_properties[] = {
>      DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
>      DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
> +    DEFINE_PROP_LINK("system-memory", PnvPsi, system_memory,
> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> @@ -701,7 +705,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
>      PnvPsi *psi = PNV_PSI(opaque);
>      Pnv9Psi *psi9 = PNV9_PSI(psi);
>      uint32_t reg = PSIHB_REG(addr);
> -    MemoryRegion *sysmem = get_system_memory();
> +    MemoryRegion *sysmem = psi->system_memory;
>  
>      switch (addr) {
>      case PSIHB9_CR:
> @@ -819,11 +823,12 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
>  static void pnv_psi_power9_reset(void *dev)
>  {
>      Pnv9Psi *psi = PNV9_PSI(dev);
> +    MemoryRegion *sysmem = PNV_PSI(psi)->system_memory;
>  
>      pnv_psi_reset(dev);
>  
>      if (memory_region_is_mapped(&psi->source.esb_mmio)) {
> -        memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
> +        memory_region_del_subregion(sysmem, &psi->source.esb_mmio);
>      }
>  }
>  
> @@ -842,6 +847,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
>      Error *local_err = NULL;
>      int i;
>  
> +    assert(psi->system_memory);
> +
>      /* This is the only device with 4k ESB pages */
>      object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
>                              &error_fatal);
Cédric Le Goater Dec. 19, 2019, 5:57 p.m. UTC | #2 
On 19/12/2019 17:01, Greg Kurz wrote:
> On Thu, 19 Dec 2019 08:29:53 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
> 
>> and use a link to pass the system memory to the device models that
>> require it to map/unmap BARs. This replace the use of get_system_memory()
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
> 
> Globally good. A few remarks, see below.
> 
>>  include/hw/ppc/pnv.h      |  2 ++
>>  include/hw/ppc/pnv_psi.h  |  1 +
>>  include/hw/ppc/pnv_xive.h |  2 ++
>>  hw/intc/pnv_xive.c        |  5 ++++-
>>  hw/ppc/pnv.c              | 31 ++++++++++++++++++++++++-------
>>  hw/ppc/pnv_psi.c          | 13 ++++++++++---
>>  6 files changed, 43 insertions(+), 11 deletions(-)
>>
>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
>> index f78fd0dd967c..f31180618672 100644
>> --- a/include/hw/ppc/pnv.h
>> +++ b/include/hw/ppc/pnv.h
>> @@ -56,6 +56,8 @@ typedef struct PnvChip {
>>      AddressSpace xscom_as;
>>  
>>      gchar        *dt_isa_nodename;
>> +
>> +    MemoryRegion *system_memory;
>>  } PnvChip;
>>  
>>  #define TYPE_PNV8_CHIP "pnv8-chip"
>> diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
>> index f0f5b5519767..f85babaff0be 100644
>> --- a/include/hw/ppc/pnv_psi.h
>> +++ b/include/hw/ppc/pnv_psi.h
>> @@ -35,6 +35,7 @@ typedef struct PnvPsi {
>>  
>>      MemoryRegion regs_mr;
>>      uint64_t bar;
>> +    MemoryRegion *system_memory;
>>  
>>      /* FSP region not supported */
>>      /* MemoryRegion fsp_mr; */
>> diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
>> index f4c7caad40ee..4d641db691c8 100644
>> --- a/include/hw/ppc/pnv_xive.h
>> +++ b/include/hw/ppc/pnv_xive.h
>> @@ -30,6 +30,8 @@ typedef struct PnvXive {
>>      /* Owning chip */
>>      struct PnvChip *chip;
>>  
>> +    MemoryRegion *system_memory;
>> +
>>      /* XSCOM addresses giving access to the controller registers */
>>      MemoryRegion  xscom_regs;
>>  
>> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
>> index a0a69b98a713..66970a60733b 100644
>> --- a/hw/intc/pnv_xive.c
>> +++ b/hw/intc/pnv_xive.c
>> @@ -853,7 +853,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
>>                                    uint64_t val, unsigned size)
>>  {
>>      PnvXive *xive = PNV_XIVE(opaque);
>> -    MemoryRegion *sysmem = get_system_memory();
>> +    MemoryRegion *sysmem = xive->system_memory;
>>      uint32_t reg = offset >> 3;
>>      bool is_chip0 = xive->chip->chip_id == 0;
>>  
>> @@ -1821,6 +1821,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
>>      Error *local_err = NULL;
>>  
>>      assert(xive->chip);
>> +    assert(xive->system_memory);
>>  
>>      /*
>>       * The XiveSource and XiveENDSource objects are realized with the
>> @@ -1937,6 +1938,8 @@ static Property pnv_xive_properties[] = {
>>      DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
>>      /* The PnvChip id identifies the XIVE interrupt controller. */
>>      DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *),
>> +    DEFINE_PROP_LINK("system-memory", PnvXive, system_memory,
>> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>  
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 855254f28263..2f611bfdda46 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -674,6 +674,7 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
>>  
>>  static void pnv_init(MachineState *machine)
>>  {
>> +    MemoryRegion *sysmem = get_system_memory();
>>      PnvMachineState *pnv = PNV_MACHINE(machine);
>>      MachineClass *mc = MACHINE_GET_CLASS(machine);
>>      MemoryRegion *ram;
>> @@ -692,7 +693,7 @@ static void pnv_init(MachineState *machine)
>>      ram = g_new(MemoryRegion, 1);
>>      memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
>>                                           machine->ram_size);
>> -    memory_region_add_subregion(get_system_memory(), 0, ram);
>> +    memory_region_add_subregion(sysmem, 0, ram);
>>  
>>      /*
>>       * Create our simple PNOR device
>> @@ -790,6 +791,12 @@ static void pnv_init(MachineState *machine)
>>                                  &error_fatal);
>>          object_property_set_int(chip, machine->smp.cores,
>>                                  "nr-cores", &error_fatal);
>> +        /*
>> +         * TODO: Only the MMIO range should be of interest for the
>> +         * controllers
>> +         */
>> +        object_property_set_link(chip, OBJECT(sysmem), "system-memory",
>> +                                 &error_abort);
> 
> Like it is done with PnvXive, it would be good to pair this with an
> assert(chip->system_memory) in pnv_chip_realize().

yes. I will do that. 

> 
>>          object_property_set_bool(chip, true, "realized", &error_fatal);
>>      }
>>      g_free(chip_typename);
>> @@ -1060,6 +1067,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>>      /* Processor Service Interface (PSI) Host Bridge */
>>      object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
>>                              "bar", &error_fatal);
>> +    object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip->system_memory),
>> +                             "system-memory", &error_abort);
>>      object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
>>      if (local_err) {
>>          error_propagate(errp, local_err);
>> @@ -1100,7 +1109,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>>      pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
>>  
>>      /* OCC SRAM model */
>> -    memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV_OCC_SENSOR_BASE(chip),
>>                                  &chip8->occ.sram_regs);
>>  
>>      /* HOMER */
>> @@ -1116,7 +1125,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
>>      pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
>>  
>>      /* Homer mmio region */
>> -    memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV_HOMER_BASE(chip),
>>                                  &chip8->homer.regs);
>>  }
>>  
>> @@ -1280,6 +1289,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>>                              "tm-bar", &error_fatal);
>>      object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
>>                               &error_abort);
>> +    object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip->system_memory),
>> +                             "system-memory", &error_abort);
>>      object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
>>                               &local_err);
>>      if (local_err) {
>> @@ -1292,6 +1303,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>>      /* Processor Service Interface (PSI) Host Bridge */
>>      object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
>>                              "bar", &error_fatal);
>> +    object_property_set_link(OBJECT(&chip9->psi), OBJECT(chip->system_memory),
>> +                             "system-memory", &error_abort);
>>      object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
>>      if (local_err) {
>>          error_propagate(errp, local_err);
>> @@ -1308,7 +1321,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>>          error_propagate(errp, local_err);
>>          return;
>>      }
>> -    memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV9_LPCM_BASE(chip),
>>                                  &chip9->lpc.xscom_regs);
>>  
>>      chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
>> @@ -1325,7 +1338,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>>      pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
>>  
>>      /* OCC SRAM model */
>> -    memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV9_OCC_SENSOR_BASE(chip),
>>                                  &chip9->occ.sram_regs);
>>  
>>      /* HOMER */
>> @@ -1341,7 +1354,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
>>      pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
>>  
>>      /* Homer mmio region */
>> -    memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV9_HOMER_BASE(chip),
>>                                  &chip9->homer.regs);
>>  }
>>  
>> @@ -1408,6 +1421,8 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
>>      /* Processor Service Interface (PSI) Host Bridge */
>>      object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
>>                              "bar", &error_fatal);
>> +    object_property_set_link(OBJECT(&chip10->psi), OBJECT(chip->system_memory),
>> +                             "system-memory", &error_abort);
>>      object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
>>                               &local_err);
>>      if (local_err) {
>> @@ -1426,7 +1441,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
>>          error_propagate(errp, local_err);
>>          return;
>>      }
>> -    memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
>> +    memory_region_add_subregion(chip->system_memory, PNV10_LPCM_BASE(chip),
>>                                  &chip10->lpc.xscom_regs);
>>  
>>      chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
>> @@ -1570,6 +1585,8 @@ static Property pnv_chip_properties[] = {
>>      DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
>>      DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
>>      DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
>> +    DEFINE_PROP_LINK("system-memory", PnvChip, system_memory,
>> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>  
>> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
>> index 75e20d9da08b..28d34e5c193a 100644
>> --- a/hw/ppc/pnv_psi.c
>> +++ b/hw/ppc/pnv_psi.c
>> @@ -126,7 +126,7 @@
>>  static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
>>  {
>>      PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
>> -    MemoryRegion *sysmem = get_system_memory();
>> +    MemoryRegion *sysmem = psi->system_memory;
>>      uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
>>  
>>      psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
>> @@ -489,6 +489,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
>>      Error *err = NULL;
>>      unsigned int i;
>>  
>> +    assert(psi->system_memory);
>> +
> 
> This should theoretically sit in a realize function of the base
> PnvPsi class. It doesn't exist but looking at the other duplicate
> code in pnv_psi_power8_realize() and pnv_psi_power9_realize(),
> eg. the reset handler, it seems it could be beneficial to
> introduce one.

I agree that Psi is a little messy. Psi8 is quite different from the 
other two. May be we should split.  

> But this is far beyond the scope of this patch, so I guess
> it is okay to keep the duplicate assert() for now.

yes.

Thanks,

C. 

>>      obj = object_property_get_link(OBJECT(dev), "xics", &err);
>>      if (!obj) {
>>          error_setg(errp, "%s: required link 'xics' not found: %s",
>> @@ -562,6 +564,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
>>  static Property pnv_psi_properties[] = {
>>      DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
>>      DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
>> +    DEFINE_PROP_LINK("system-memory", PnvPsi, system_memory,
>> +                     TYPE_MEMORY_REGION, MemoryRegion *),
>>      DEFINE_PROP_END_OF_LIST(),
>>  };
>>  
>> @@ -701,7 +705,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
>>      PnvPsi *psi = PNV_PSI(opaque);
>>      Pnv9Psi *psi9 = PNV9_PSI(psi);
>>      uint32_t reg = PSIHB_REG(addr);
>> -    MemoryRegion *sysmem = get_system_memory();
>> +    MemoryRegion *sysmem = psi->system_memory;
>>  
>>      switch (addr) {
>>      case PSIHB9_CR:
>> @@ -819,11 +823,12 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
>>  static void pnv_psi_power9_reset(void *dev)
>>  {
>>      Pnv9Psi *psi = PNV9_PSI(dev);
>> +    MemoryRegion *sysmem = PNV_PSI(psi)->system_memory;
>>  
>>      pnv_psi_reset(dev);
>>  
>>      if (memory_region_is_mapped(&psi->source.esb_mmio)) {
>> -        memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
>> +        memory_region_del_subregion(sysmem, &psi->source.esb_mmio);
>>      }
>>  }
>>  
>> @@ -842,6 +847,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
>>      Error *local_err = NULL;
>>      int i;
>>  
>> +    assert(psi->system_memory);
>> +
>>      /* This is the only device with 4k ESB pages */
>>      object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
>>                              &error_fatal);
>
diff mbox series

Patch

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f78fd0dd967c..f31180618672 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -56,6 +56,8 @@  typedef struct PnvChip {
     AddressSpace xscom_as;
 
     gchar        *dt_isa_nodename;
+
+    MemoryRegion *system_memory;
 } PnvChip;
 
 #define TYPE_PNV8_CHIP "pnv8-chip"
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index f0f5b5519767..f85babaff0be 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -35,6 +35,7 @@  typedef struct PnvPsi {
 
     MemoryRegion regs_mr;
     uint64_t bar;
+    MemoryRegion *system_memory;
 
     /* FSP region not supported */
     /* MemoryRegion fsp_mr; */
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index f4c7caad40ee..4d641db691c8 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -30,6 +30,8 @@  typedef struct PnvXive {
     /* Owning chip */
     struct PnvChip *chip;
 
+    MemoryRegion *system_memory;
+
     /* XSCOM addresses giving access to the controller registers */
     MemoryRegion  xscom_regs;
 
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index a0a69b98a713..66970a60733b 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -853,7 +853,7 @@  static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
                                   uint64_t val, unsigned size)
 {
     PnvXive *xive = PNV_XIVE(opaque);
-    MemoryRegion *sysmem = get_system_memory();
+    MemoryRegion *sysmem = xive->system_memory;
     uint32_t reg = offset >> 3;
     bool is_chip0 = xive->chip->chip_id == 0;
 
@@ -1821,6 +1821,7 @@  static void pnv_xive_realize(DeviceState *dev, Error **errp)
     Error *local_err = NULL;
 
     assert(xive->chip);
+    assert(xive->system_memory);
 
     /*
      * The XiveSource and XiveENDSource objects are realized with the
@@ -1937,6 +1938,8 @@  static Property pnv_xive_properties[] = {
     DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0),
     /* The PnvChip id identifies the XIVE interrupt controller. */
     DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *),
+    DEFINE_PROP_LINK("system-memory", PnvXive, system_memory,
+                     TYPE_MEMORY_REGION, MemoryRegion *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 855254f28263..2f611bfdda46 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -674,6 +674,7 @@  static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
 
 static void pnv_init(MachineState *machine)
 {
+    MemoryRegion *sysmem = get_system_memory();
     PnvMachineState *pnv = PNV_MACHINE(machine);
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     MemoryRegion *ram;
@@ -692,7 +693,7 @@  static void pnv_init(MachineState *machine)
     ram = g_new(MemoryRegion, 1);
     memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
                                          machine->ram_size);
-    memory_region_add_subregion(get_system_memory(), 0, ram);
+    memory_region_add_subregion(sysmem, 0, ram);
 
     /*
      * Create our simple PNOR device
@@ -790,6 +791,12 @@  static void pnv_init(MachineState *machine)
                                 &error_fatal);
         object_property_set_int(chip, machine->smp.cores,
                                 "nr-cores", &error_fatal);
+        /*
+         * TODO: Only the MMIO range should be of interest for the
+         * controllers
+         */
+        object_property_set_link(chip, OBJECT(sysmem), "system-memory",
+                                 &error_abort);
         object_property_set_bool(chip, true, "realized", &error_fatal);
     }
     g_free(chip_typename);
@@ -1060,6 +1067,8 @@  static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
     /* Processor Service Interface (PSI) Host Bridge */
     object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
                             "bar", &error_fatal);
+    object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip->system_memory),
+                             "system-memory", &error_abort);
     object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
@@ -1100,7 +1109,7 @@  static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
     pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
 
     /* OCC SRAM model */
-    memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV_OCC_SENSOR_BASE(chip),
                                 &chip8->occ.sram_regs);
 
     /* HOMER */
@@ -1116,7 +1125,7 @@  static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
     pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
 
     /* Homer mmio region */
-    memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV_HOMER_BASE(chip),
                                 &chip8->homer.regs);
 }
 
@@ -1280,6 +1289,8 @@  static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
                             "tm-bar", &error_fatal);
     object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
                              &error_abort);
+    object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip->system_memory),
+                             "system-memory", &error_abort);
     object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
                              &local_err);
     if (local_err) {
@@ -1292,6 +1303,8 @@  static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
     /* Processor Service Interface (PSI) Host Bridge */
     object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
                             "bar", &error_fatal);
+    object_property_set_link(OBJECT(&chip9->psi), OBJECT(chip->system_memory),
+                             "system-memory", &error_abort);
     object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
@@ -1308,7 +1321,7 @@  static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
         error_propagate(errp, local_err);
         return;
     }
-    memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV9_LPCM_BASE(chip),
                                 &chip9->lpc.xscom_regs);
 
     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
@@ -1325,7 +1338,7 @@  static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
     pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
 
     /* OCC SRAM model */
-    memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV9_OCC_SENSOR_BASE(chip),
                                 &chip9->occ.sram_regs);
 
     /* HOMER */
@@ -1341,7 +1354,7 @@  static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
     pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
 
     /* Homer mmio region */
-    memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV9_HOMER_BASE(chip),
                                 &chip9->homer.regs);
 }
 
@@ -1408,6 +1421,8 @@  static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
     /* Processor Service Interface (PSI) Host Bridge */
     object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
                             "bar", &error_fatal);
+    object_property_set_link(OBJECT(&chip10->psi), OBJECT(chip->system_memory),
+                             "system-memory", &error_abort);
     object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
                              &local_err);
     if (local_err) {
@@ -1426,7 +1441,7 @@  static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
         error_propagate(errp, local_err);
         return;
     }
-    memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
+    memory_region_add_subregion(chip->system_memory, PNV10_LPCM_BASE(chip),
                                 &chip10->lpc.xscom_regs);
 
     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
@@ -1570,6 +1585,8 @@  static Property pnv_chip_properties[] = {
     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
+    DEFINE_PROP_LINK("system-memory", PnvChip, system_memory,
+                     TYPE_MEMORY_REGION, MemoryRegion *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 75e20d9da08b..28d34e5c193a 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -126,7 +126,7 @@ 
 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
 {
     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
-    MemoryRegion *sysmem = get_system_memory();
+    MemoryRegion *sysmem = psi->system_memory;
     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
 
     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
@@ -489,6 +489,8 @@  static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
     Error *err = NULL;
     unsigned int i;
 
+    assert(psi->system_memory);
+
     obj = object_property_get_link(OBJECT(dev), "xics", &err);
     if (!obj) {
         error_setg(errp, "%s: required link 'xics' not found: %s",
@@ -562,6 +564,8 @@  static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 static Property pnv_psi_properties[] = {
     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
+    DEFINE_PROP_LINK("system-memory", PnvPsi, system_memory,
+                     TYPE_MEMORY_REGION, MemoryRegion *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -701,7 +705,7 @@  static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
     PnvPsi *psi = PNV_PSI(opaque);
     Pnv9Psi *psi9 = PNV9_PSI(psi);
     uint32_t reg = PSIHB_REG(addr);
-    MemoryRegion *sysmem = get_system_memory();
+    MemoryRegion *sysmem = psi->system_memory;
 
     switch (addr) {
     case PSIHB9_CR:
@@ -819,11 +823,12 @@  static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
 static void pnv_psi_power9_reset(void *dev)
 {
     Pnv9Psi *psi = PNV9_PSI(dev);
+    MemoryRegion *sysmem = PNV_PSI(psi)->system_memory;
 
     pnv_psi_reset(dev);
 
     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
-        memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
+        memory_region_del_subregion(sysmem, &psi->source.esb_mmio);
     }
 }
 
@@ -842,6 +847,8 @@  static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
     Error *local_err = NULL;
     int i;
 
+    assert(psi->system_memory);
+
     /* This is the only device with 4k ESB pages */
     object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
                             &error_fatal);