| Message ID | 20191226185148.3764251-2-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 3aec743d69822d22d4a5b60deb9518ed8be6fa67 |
| Headers | show |
| Series | RTL8211F: RGMII RX/TX delay configuration improvements | expand |
On 12/26/2019 10:51 AM, Martin Blumenstingl wrote: > RGMII requires a delay of 2ns between the data and the clock signal. > There are at least three ways this can happen. One possibility is by > having the PHY generate this delay. > This is a common source for problems (for example with slow TX speeds or > packet loss when sending data). The TX delay configuration of the > RTL8211F PHY can be set either by pin-strappping the RXD1 pin (HIGH > means enabled, LOW means disabled) or through configuring a paged > register. The setting from the RXD1 pin is also reflected in the > register. > > Add debug logging to the TX delay configuration on RTL8211F so it's > easier to spot these issues (for example if the TX delay is enabled for > both, the RTL8211F PHY and the MAC). > This is especially helpful because there is no public datasheet for the > RTL8211F PHY available with all the RX/TX delay specifics. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 476db5345e1a..879ca37c8508 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -171,7 +171,9 @@ static int rtl8211c_config_init(struct phy_device *phydev) static int rtl8211f_config_init(struct phy_device *phydev) { + struct device *dev = &phydev->mdio.dev; u16 val; + int ret; /* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin. @@ -189,7 +191,22 @@ static int rtl8211f_config_init(struct phy_device *phydev) return 0; } - return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); + ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, + val); + if (ret < 0) { + dev_err(dev, "Failed to update the TX delay register\n"); + return ret; + } else if (ret) { + dev_dbg(dev, + "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", + val ? "Enabling" : "Disabling"); + } else { + dev_dbg(dev, + "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", + val ? "enabled" : "disabled"); + } + + return 0; } static int rtl8211e_config_init(struct phy_device *phydev)
RGMII requires a delay of 2ns between the data and the clock signal. There are at least three ways this can happen. One possibility is by having the PHY generate this delay. This is a common source for problems (for example with slow TX speeds or packet loss when sending data). The TX delay configuration of the RTL8211F PHY can be set either by pin-strappping the RXD1 pin (HIGH means enabled, LOW means disabled) or through configuring a paged register. The setting from the RXD1 pin is also reflected in the register. Add debug logging to the TX delay configuration on RTL8211F so it's easier to spot these issues (for example if the TX delay is enabled for both, the RTL8211F PHY and the MAC). This is especially helpful because there is no public datasheet for the RTL8211F PHY available with all the RX/TX delay specifics. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/net/phy/realtek.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)