diff mbox series

KVM: VMX: Rename define to CPU_BASED_USE_TSC_OFFSETTING

Message ID 20200113185216.GQ13310@zn.tnic (mailing list archive)
State New, archived
Headers show
Series KVM: VMX: Rename define to CPU_BASED_USE_TSC_OFFSETTING | expand

Commit Message

Borislav Petkov Jan. 13, 2020, 6:52 p.m. UTC 
On Mon, Jan 13, 2020 at 10:42:17AM -0800, Sean Christopherson wrote:
> > Doesn't bother me, I could do it in a patch ontop. But your call.
> 
> No objection here.

Something like this:

---
From: Borislav Petkov <bp@suse.de>

... so that "offsetting" is spelled the same as the respective VMX feature
bit VMX_FEATURE_TSC_OFFSETTING.

No functional changes.

Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/include/asm/vmx.h                               | 2 +-
 arch/x86/kvm/vmx/nested.c                                | 8 ++++----
 arch/x86/kvm/vmx/vmx.c                                   | 6 +++---
 tools/testing/selftests/kvm/include/x86_64/vmx.h         | 2 +-
 tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c | 2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

Comments

Sean Christopherson Jan. 13, 2020, 8:16 p.m. UTC | #1 
On Mon, Jan 13, 2020 at 07:52:16PM +0100, Borislav Petkov wrote:
> On Mon, Jan 13, 2020 at 10:42:17AM -0800, Sean Christopherson wrote:
> > > Doesn't bother me, I could do it in a patch ontop. But your call.
> > 
> > No objection here.
> 
> Something like this:
> 
> ---
> From: Borislav Petkov <bp@suse.de>
> 
> ... so that "offsetting" is spelled the same as the respective VMX feature
> bit VMX_FEATURE_TSC_OFFSETTING.
> 
> No functional changes.
> 
> Signed-off-by: Borislav Petkov <bp@suse.de>
> ---

Reviewed-and-tested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Borislav Petkov Jan. 14, 2020, 9:31 a.m. UTC | #2 
On Mon, Jan 13, 2020 at 12:16:10PM -0800, Sean Christopherson wrote:
> On Mon, Jan 13, 2020 at 07:52:16PM +0100, Borislav Petkov wrote:
> > On Mon, Jan 13, 2020 at 10:42:17AM -0800, Sean Christopherson wrote:
> > > > Doesn't bother me, I could do it in a patch ontop. But your call.
> > > 
> > > No objection here.
> > 
> > Something like this:
> > 
> > ---
> > From: Borislav Petkov <bp@suse.de>
> > 
> > ... so that "offsetting" is spelled the same as the respective VMX feature
> > bit VMX_FEATURE_TSC_OFFSETTING.
> > 
> > No functional changes.
> > 
> > Signed-off-by: Borislav Petkov <bp@suse.de>
> > ---
> 
> Reviewed-and-tested-by: Sean Christopherson <sean.j.christopherson@intel.com>

Yah, so I tried to do a test-merge with linux-next to see what surprises should
I be prepared for and there's the first one:

5e3d394fdd9e ("KVM: VMX: Fix the spelling of CPU_BASED_USE_TSC_OFFSETTING")

which is already in Paolo's tree. Dropping it on my side.
Sean Christopherson Jan. 14, 2020, 5:27 p.m. UTC | #3 
On Tue, Jan 14, 2020 at 10:31:38AM +0100, Borislav Petkov wrote:
> On Mon, Jan 13, 2020 at 12:16:10PM -0800, Sean Christopherson wrote:
> > On Mon, Jan 13, 2020 at 07:52:16PM +0100, Borislav Petkov wrote:
> > > On Mon, Jan 13, 2020 at 10:42:17AM -0800, Sean Christopherson wrote:
> > > > > Doesn't bother me, I could do it in a patch ontop. But your call.
> > > > 
> > > > No objection here.
> > > 
> > > Something like this:
> > > 
> > > ---
> > > From: Borislav Petkov <bp@suse.de>
> > > 
> > > ... so that "offsetting" is spelled the same as the respective VMX feature
> > > bit VMX_FEATURE_TSC_OFFSETTING.
> > > 
> > > No functional changes.
> > > 
> > > Signed-off-by: Borislav Petkov <bp@suse.de>
> > > ---
> > 
> > Reviewed-and-tested-by: Sean Christopherson <sean.j.christopherson@intel.com>
> 
> Yah, so I tried to do a test-merge with linux-next to see what surprises should
> I be prepared for and there's the first one:
> 
> 5e3d394fdd9e ("KVM: VMX: Fix the spelling of CPU_BASED_USE_TSC_OFFSETTING")
> 
> which is already in Paolo's tree. Dropping it on my side.

Doh, now that you point it out, I remember that patch going by.  Sorry I
didn't recall it earlier.

Thanks for your help!
diff mbox series

Patch

diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 9fbba31be825..6df8b3b94483 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -23,7 +23,7 @@ 
  * Definitions of Primary Processor-Based VM-Execution Controls.
  */
 #define CPU_BASED_VIRTUAL_INTR_PENDING          VMCS_CONTROL_BIT(VIRTUAL_INTR_PENDING)
-#define CPU_BASED_USE_TSC_OFFSETING             VMCS_CONTROL_BIT(TSC_OFFSETTING)
+#define CPU_BASED_USE_TSC_OFFSETTING             VMCS_CONTROL_BIT(TSC_OFFSETTING)
 #define CPU_BASED_HLT_EXITING                   VMCS_CONTROL_BIT(HLT_EXITING)
 #define CPU_BASED_INVLPG_EXITING                VMCS_CONTROL_BIT(INVLPG_EXITING)
 #define CPU_BASED_MWAIT_EXITING                 VMCS_CONTROL_BIT(MWAIT_EXITING)
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 6879966b7648..d466666b1de9 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -3230,7 +3230,7 @@  enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
 	}
 
 	enter_guest_mode(vcpu);
-	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
+	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
 		vcpu->arch.tsc_offset += vmcs12->tsc_offset;
 
 	if (prepare_vmcs02(vcpu, vmcs12, &exit_qual))
@@ -3294,7 +3294,7 @@  enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
 	 * 26.7 "VM-entry failures during or after loading guest state".
 	 */
 vmentry_fail_vmexit_guest_mode:
-	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
+	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
 		vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
 	leave_guest_mode(vcpu);
 
@@ -4209,7 +4209,7 @@  void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
 	if (nested_cpu_has_preemption_timer(vmcs12))
 		hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
 
-	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
+	if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)
 		vcpu->arch.tsc_offset -= vmcs12->tsc_offset;
 
 	if (likely(!vmx->fail)) {
@@ -6016,7 +6016,7 @@  void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
 		CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
 	msrs->procbased_ctls_high &=
 		CPU_BASED_VIRTUAL_INTR_PENDING |
-		CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
+		CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETTING |
 		CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
 		CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
 		CPU_BASED_CR3_STORE_EXITING |
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index cdb4bf50ee14..e543232a28b2 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1716,7 +1716,7 @@  static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
 	struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
 	if (is_guest_mode(vcpu) &&
-	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
+	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
 		return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
 
 	return vcpu->arch.tsc_offset;
@@ -1734,7 +1734,7 @@  static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 	 * to the newly set TSC to get L2's TSC.
 	 */
 	if (is_guest_mode(vcpu) &&
-	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
+	    (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING))
 		g_tsc_offset = vmcs12->tsc_offset;
 
 	trace_kvm_write_tsc_offset(vcpu->vcpu_id,
@@ -2322,7 +2322,7 @@  static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
 	      CPU_BASED_CR3_STORE_EXITING |
 	      CPU_BASED_UNCOND_IO_EXITING |
 	      CPU_BASED_MOV_DR_EXITING |
-	      CPU_BASED_USE_TSC_OFFSETING |
+	      CPU_BASED_USE_TSC_OFFSETTING |
 	      CPU_BASED_MWAIT_EXITING |
 	      CPU_BASED_MONITOR_EXITING |
 	      CPU_BASED_INVLPG_EXITING |
diff --git a/tools/testing/selftests/kvm/include/x86_64/vmx.h b/tools/testing/selftests/kvm/include/x86_64/vmx.h
index f52e0ba84fed..969a0f0c2ec0 100644
--- a/tools/testing/selftests/kvm/include/x86_64/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86_64/vmx.h
@@ -19,7 +19,7 @@ 
  * Definitions of Primary Processor-Based VM-Execution Controls.
  */
 #define CPU_BASED_VIRTUAL_INTR_PENDING		0x00000004
-#define CPU_BASED_USE_TSC_OFFSETING		0x00000008
+#define CPU_BASED_USE_TSC_OFFSETTING		0x00000008
 #define CPU_BASED_HLT_EXITING			0x00000080
 #define CPU_BASED_INVLPG_EXITING		0x00000200
 #define CPU_BASED_MWAIT_EXITING			0x00000400
diff --git a/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c b/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
index 5590fd2bcf87..69e482a95c47 100644
--- a/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
+++ b/tools/testing/selftests/kvm/x86_64/vmx_tsc_adjust_test.c
@@ -98,7 +98,7 @@  static void l1_guest_code(struct vmx_pages *vmx_pages)
 	prepare_vmcs(vmx_pages, l2_guest_code,
 		     &l2_guest_stack[L2_GUEST_STACK_SIZE]);
 	control = vmreadz(CPU_BASED_VM_EXEC_CONTROL);
-	control |= CPU_BASED_USE_MSR_BITMAPS | CPU_BASED_USE_TSC_OFFSETING;
+	control |= CPU_BASED_USE_MSR_BITMAPS | CPU_BASED_USE_TSC_OFFSETTING;
 	vmwrite(CPU_BASED_VM_EXEC_CONTROL, control);
 	vmwrite(TSC_OFFSET, TSC_OFFSET_VALUE);