Message ID | 20200128003707.17028-1-ianjiang.ict@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2] riscv: Add helper to make NaN-boxing for FP register | expand |
On Mon, Jan 27, 2020 at 4:37 PM Ian Jiang <ianjiang.ict@gmail.com> wrote: > > The function that makes NaN-boxing when a 32-bit value is assigned > to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). > Then it is applied in translating of the FLW instruction. > > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c > index e23cd639a6..3bfd8881e7 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -23,6 +23,20 @@ > return false; \ > } while (0) > > +/* > + * RISC-V requires NaN-boxing of narrower width floating > + * point values. This applies when a 32-bit value is > + * assigned to a 64-bit FP register. Thus this does not > + * apply when the RVD extension is not present. > + */ > +static void gen_nanbox_fpr(DisasContext *ctx, int regno) > +{ > + if (has_ext(ctx, RVD)) { > + tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], > + MAKE_64BIT_MASK(32, 32)); > + } > +} > + > static bool trans_flw(DisasContext *ctx, arg_flw *a) > { > TCGv t0 = tcg_temp_new(); > @@ -32,8 +46,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) > tcg_gen_addi_tl(t0, t0, a->imm); > > tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); > - /* RISC-V requires NaN-boxing of narrower width floating point values */ > - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL); > + gen_nanbox_fpr(ctx, a->rd); > > tcg_temp_free(t0); > mark_fs_dirty(ctx); > -- > 2.17.1 > >
On 1/27/20 4:37 PM, Ian Jiang wrote: > The function that makes NaN-boxing when a 32-bit value is assigned > to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). > Then it is applied in translating of the FLW instruction. > > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
ping ? Could this be merged ? Chih-Min Chao On Wed, Jan 29, 2020 at 3:43 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 1/27/20 4:37 PM, Ian Jiang wrote: > > The function that makes NaN-boxing when a 32-bit value is assigned > > to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). > > Then it is applied in translating of the FLW instruction. > > > > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> > > --- > > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- > > 1 file changed, 15 insertions(+), 2 deletions(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > > > r~ > >
On Tue, Jun 9, 2020 at 3:08 AM Chih-Min Chao <chihmin.chao@sifive.com> wrote: > > ping ? Could this be merged ? Applied to the RISC-V tree. Alistair > > > Chih-Min Chao > > > > On Wed, Jan 29, 2020 at 3:43 AM Richard Henderson <richard.henderson@linaro.org> wrote: >> >> On 1/27/20 4:37 PM, Ian Jiang wrote: >> > The function that makes NaN-boxing when a 32-bit value is assigned >> > to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). >> > Then it is applied in translating of the FLW instruction. >> > >> > Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> >> > --- >> > target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- >> > 1 file changed, 15 insertions(+), 2 deletions(-) >> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> >> >> >> r~ >>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index e23cd639a6..3bfd8881e7 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -23,6 +23,20 @@ return false; \ } while (0) +/* + * RISC-V requires NaN-boxing of narrower width floating + * point values. This applies when a 32-bit value is + * assigned to a 64-bit FP register. Thus this does not + * apply when the RVD extension is not present. + */ +static void gen_nanbox_fpr(DisasContext *ctx, int regno) +{ + if (has_ext(ctx, RVD)) { + tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], + MAKE_64BIT_MASK(32, 32)); + } +} + static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); @@ -32,8 +46,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - /* RISC-V requires NaN-boxing of narrower width floating point values */ - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL); + gen_nanbox_fpr(ctx, a->rd); tcg_temp_free(t0); mark_fs_dirty(ctx);
The function that makes NaN-boxing when a 32-bit value is assigned to a 64-bit FP register is split out to a helper gen_nanbox_fpr(). Then it is applied in translating of the FLW instruction. Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com> --- target/riscv/insn_trans/trans_rvf.inc.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)