| Message ID | 1580308205-20435-6-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Pavel Machek |
| Headers | show |
| Series | Renesas RZ/G2N extend peripheral support | expand |
On Wed 2020-01-29 14:29:58, Biju Das wrote: > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream. > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N > SoC (a.k.a. r8a774b1). I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I still don't know what "MSIOF" stands for, if anything. Best regards, Pavel
Hi Pavel, > -----Original Message----- > From: cip-dev <cip-dev-bounces@lists.cip-project.org> On Behalf Of Pavel > Machek > Sent: 30 January 2020 19:27 > To: Biju Das <biju.das@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org > Subject: Re: [cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: > r8a774b1: Add all MSIOF nodes > > On Wed 2020-01-29 14:29:58, Biju Das wrote: > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream. > > > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC > > (a.k.a. r8a774b1). > > I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I still > don't know what "MSIOF" stands for, if anything. > "MSIOF" stands for clock-synchronized serial interface with FIFO, this interface supports IIS and SPI serial formats (master and slave mode). ATM only SPI master mode is supported in mainline Kernel. Cheers, --Prabhakar > Best regards, > Pavel > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
Hi! > > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream. > > > > > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC > > > (a.k.a. r8a774b1). > > > > I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I still > > don't know what "MSIOF" stands for, if anything. > > > "MSIOF" stands for clock-synchronized serial interface with FIFO, this interface supports IIS and > SPI serial formats (master and slave mode). ATM only SPI master mode is supported in mainline > Kernel. Ok, I can imagine that. But is "MSIOF" an acronym, and if so, what does it stand for? Best regards, Pavel
Hello Pavel, > From: cip-dev <cip-dev-bounces@lists.cip-project.org> On Behalf Of Pavel > Machek > Sent: 02 February 2020 18:01 > > Hi! > > > > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream. > > > > > > > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC > > > > (a.k.a. r8a774b1). > > > > > > I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I > still > > > don't know what "MSIOF" stands for, if anything. > > > > > "MSIOF" stands for clock-synchronized serial interface with FIFO, this > interface supports IIS and > > SPI serial formats (master and slave mode). ATM only SPI master mode is > supported in mainline > > Kernel. > > Ok, I can imagine that. But is "MSIOF" an acronym, and if so, what > does it stand for? To be honest, even I'm not sure what the acronym is meant to mean (or even if there is a direct meaning), but the 'long' name for the IP block is "Clock-Synchronized Serial Interface with FIFO". Kind regards, Chris > > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index de904426..aede2b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -650,6 +650,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */