| Message ID | 20191218143416.v3.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 457622d9f99b9b2b44375d7e5e95cde5f66910f9 |
| Headers | show |
| Series | drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP | expand |
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote: > At least one panel hooked up to the bridge (AUO B116XAK01) only > supports 1 lane of DP. Let's read this information and stop > hardcoding 4 DP lanes. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Tested-by: Rob Clark <robdclark@gmail.com> > Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes in v3: None > Changes in v2: None > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 32 +++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index d55d19759796..0fc9e97b2d98 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) > goto err_dsi_host; > } > > - /* TODO: setting to 4 lanes always for now */ > - pdata->dp_lanes = 4; > + /* TODO: setting to 4 MIPI lanes always for now */ > dsi->lanes = 4; > dsi->format = MIPI_DSI_FMT_RGB888; > dsi->mode_flags = MIPI_DSI_MODE_VIDEO; > @@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) > usleep_range(10000, 10500); /* 10ms delay recommended by spec */ > } > > +static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) > +{ > + u8 data; > + int ret; > + > + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); > + if (ret != 1) { > + DRM_DEV_ERROR(pdata->dev, > + "Can't read lane count (%d); assuming 4\n", ret); > + return 4; > + } > + > + return data & DP_LANE_COUNT_MASK; > +} > + > static void ti_sn_bridge_enable(struct drm_bridge *bridge) > { > struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); > unsigned int val; > int ret; > > + /* > + * Run with the maximum number of lanes that the DP sink supports. > + * > + * Depending use cases, we might want to revisit this later because: > + * - It's plausible that someone may have run fewer lines to the > + * sink than the sink actually supports, assuming that the lines > + * will just be driven at a higher rate. > + * - The DP spec seems to indicate that it's more important to minimize > + * the number of lanes than the link rate. > + * > + * If we do revisit, it would be important to measure the power impact. > + */ > + pdata->dp_lanes = ti_sn_get_max_lanes(pdata); > + > /* DSI_A lane config */ > val = CHA_DSI_LANES(4 - pdata->dsi->lanes); > regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, > -- > 2.24.1.735.g03f4e72817-goog >
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d55d19759796..0fc9e97b2d98 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) goto err_dsi_host; } - /* TODO: setting to 4 lanes always for now */ - pdata->dp_lanes = 4; + /* TODO: setting to 4 MIPI lanes always for now */ dsi->lanes = 4; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO; @@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) usleep_range(10000, 10500); /* 10ms delay recommended by spec */ } +static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) +{ + u8 data; + int ret; + + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read lane count (%d); assuming 4\n", ret); + return 4; + } + + return data & DP_LANE_COUNT_MASK; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); unsigned int val; int ret; + /* + * Run with the maximum number of lanes that the DP sink supports. + * + * Depending use cases, we might want to revisit this later because: + * - It's plausible that someone may have run fewer lines to the + * sink than the sink actually supports, assuming that the lines + * will just be driven at a higher rate. + * - The DP spec seems to indicate that it's more important to minimize + * the number of lanes than the link rate. + * + * If we do revisit, it would be important to measure the power impact. + */ + pdata->dp_lanes = ti_sn_get_max_lanes(pdata); + /* DSI_A lane config */ val = CHA_DSI_LANES(4 - pdata->dsi->lanes); regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,