| Message ID | 20200129234640.8147-7-sean.j.christopherson@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: x86: Purge kvm_x86_ops->*_supported() | expand |
Sean Christopherson <sean.j.christopherson@intel.com> writes: > Move the MSR_IA32_BNDCFGS existence check into vendor code by way of > ->has_virtualized_msr(). AMD does not support MPX, and given that Intel > is in the process of removing MPX, it's extremely unlikely AMD will ever > support MPX. > > Note, invoking ->has_virtualized_msr() requires an extra retpoline, but > kvm_init_msr_list() is not a hot path. As alluded to above, the > motivation is to quarantine MPX as much as possible. > > No functional change intended. > > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> > --- > arch/x86/kvm/svm.c | 2 ++ > arch/x86/kvm/vmx/vmx.c | 2 ++ > arch/x86/kvm/x86.c | 4 ---- > 3 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c > index 4c8427f57b71..504118c49f46 100644 > --- a/arch/x86/kvm/svm.c > +++ b/arch/x86/kvm/svm.c > @@ -5990,6 +5990,8 @@ static bool svm_has_virtualized_msr(u32 index) > switch (index) { > case MSR_TSC_AUX: > return boot_cpu_has(X86_FEATURE_RDTSCP); > + case MSR_IA32_BNDCFGS: > + return false; > default: > break; > } > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 9588914e941e..dbeef64f7409 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -6279,6 +6279,8 @@ static bool vmx_has_virtualized_msr(u32 index) > switch (index) { > case MSR_TSC_AUX: > return cpu_has_vmx_rdtscp(); > + case MSR_IA32_BNDCFGS: > + return kvm_mpx_supported(); > default: > break; > } > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index a8619c52ea86..70cbb9164088 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -5237,10 +5237,6 @@ static void kvm_init_msr_list(void) > * to the guests in some cases. > */ > switch (msr_index) { > - case MSR_IA32_BNDCFGS: > - if (!kvm_mpx_supported()) > - continue; > - break; > case MSR_IA32_RTIT_CTL: > case MSR_IA32_RTIT_STATUS: > if (!kvm_x86_ops->pt_supported()) Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 4c8427f57b71..504118c49f46 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -5990,6 +5990,8 @@ static bool svm_has_virtualized_msr(u32 index) switch (index) { case MSR_TSC_AUX: return boot_cpu_has(X86_FEATURE_RDTSCP); + case MSR_IA32_BNDCFGS: + return false; default: break; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 9588914e941e..dbeef64f7409 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6279,6 +6279,8 @@ static bool vmx_has_virtualized_msr(u32 index) switch (index) { case MSR_TSC_AUX: return cpu_has_vmx_rdtscp(); + case MSR_IA32_BNDCFGS: + return kvm_mpx_supported(); default: break; } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a8619c52ea86..70cbb9164088 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5237,10 +5237,6 @@ static void kvm_init_msr_list(void) * to the guests in some cases. */ switch (msr_index) { - case MSR_IA32_BNDCFGS: - if (!kvm_mpx_supported()) - continue; - break; case MSR_IA32_RTIT_CTL: case MSR_IA32_RTIT_STATUS: if (!kvm_x86_ops->pt_supported())
Move the MSR_IA32_BNDCFGS existence check into vendor code by way of ->has_virtualized_msr(). AMD does not support MPX, and given that Intel is in the process of removing MPX, it's extremely unlikely AMD will ever support MPX. Note, invoking ->has_virtualized_msr() requires an extra retpoline, but kvm_init_msr_list() is not a hot path. As alluded to above, the motivation is to quarantine MPX as much as possible. No functional change intended. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- arch/x86/kvm/svm.c | 2 ++ arch/x86/kvm/vmx/vmx.c | 2 ++ arch/x86/kvm/x86.c | 4 ---- 3 files changed, 4 insertions(+), 4 deletions(-)