| Message ID | 1580235801-4129-3-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add Tegra driver for video capture | expand |
Quoting Sowjanya Komatineni (2020-01-28 10:23:18) > Tegra210 CSI hardware internally uses PLLD for internal test pattern > generator logic. > > PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD > out to CSI during TPG mode. > > This patch adds this CSI TPG clock gate to Tegra210 clock driver > to allow Tegra video driver to ungate CSI TPG clock during TPG mode > and gate during non TPG mode. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 762cd186f714..e66498b5fd6f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3041,6 +3041,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d_out0", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+)